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31st Annual International Symposium on Computer Architecture (ISCA'04)
Transactional Memory Coherence and Consistency
M?nchen, Germany
June 19-June 23
ISBN: 0-7695-2143-6
Lance Hammond, Stanford University
Vicky Wong, Stanford University
Mike Chen, Stanford University
Brian D. Carlstrom, Stanford University
John D. Davis, Stanford University
Ben Hertzberg, Stanford University
Manohar K. Prabhu, Stanford University
Honggo Wijaya, Stanford University
Christos Kozyrakis, Stanford University
Kunle Olukotun, Stanford University
In this paper, we propos a new shared memory model: Transactional memory Coherence and Consistency (TCC). TCC provides a model in which atomic transactions are always the basic unit of parallel work, communication, memory coherence, and memory reference consistency. TCC greatly simplifies parallel software by eliminating the need for synchronization using conventional locks and semaphores, along with their complexities.
TCC hardware must combine all writes from each transaction region in a program into a single packet and broadcast this packet to the permanent shared memory state atomically as a large block. This simplifies the coherence hardware because it reduces the need for small, low-latency messages and completely eliminates the need for conventional snoopy cache coherence protocols, as multiple speculatively written versions of a cache line may safely coexist within the system. Meanwhile, automatic, hardware-controlled rollback of speculative transactions resolves any correctness violations that may occur when several processors attempt to read and write the same data simultaneously. The cost of this simplified scheme is higher interprocessor bandwidth.
To explore the costs and benefits of TCC, we study the characterisitcs of an optimal transaction-based memory system, and examine how different design parameters could affect the performance of real systems. Across a spectrum of applications, the TCC model itself did not limit available parallelism. Most applications are easily divided into transactions requiring only small write buffers, on the order of 4-8 KB. The broadcast requirements of TCC are high, but are well within the capabilities of CMPs and small-scale SMPs with high-speed interconnects.
Citation:
Lance Hammond, Vicky Wong, Mike Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, Kunle Olukotun, "Transactional Memory Coherence and Consistency," isca, pp.102, 31st Annual International Symposium on Computer Architecture (ISCA'04), 2004
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