CSDL - Proceedings I

Message from the Program Chair (PDF)

pp. ix

Organizing Committee (PDF)

pp. x

Steering Committee (PDF)

pp. xi

Program Committee (PDF)

pp. xii

Reviewers (PDF)

pp. xiii

Session 1: Processor Pipelines

The Optimum Pipeline Depth for a Microprocessor (Abstract)

A. Hartstein, IBM -T.J.Watson Research Center

Thomas R. Puzak, IBM -T.J.Watson Research Center

pp. 0007

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The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays (Abstract)

M. S. Hrishikesh, University of Texas at Austin

Doug Burger, University of Texas at Austin

Stephen W. Keckler, University of Texas at Austin

Premkishore Shivakumar, University of Texas at Austin

Norman P. Jouppi, Compaq Computer Corporation

Keith I. Farkas, Compaq Computer Corporation

pp. 0014

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Increasing Processor Performance by Implementing Deeper Pipelines (Abstract)

Eric Sprangle, Intel Corporation

Doug Carmean, Intel Corporation

pp. 0025

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Session 2: Processor Scheduling

Efficient Dynamic Scheduling Through Tag Elimination (Abstract)

Dan Ernst, University of Michigan

Todd Austin, University of Michigan

pp. 0037

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Slack: Maximizing Performance Under Technological Constraints (Abstract)

Brian Fields, University of Wisconsin at Madison

Rastislav Bodik, University of Wisconsin at Madison

Mark D. Hill, University of Wisconsin at Madison

pp. 0047

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A Large, Fast Instruction Window for Tolerating Cache Misses (Abstract)

Alvin R. Lebeck, Duke University

Tong Li, Duke University

Eric Rotenberg, Duke University

Jinson Koppanalil, North Carolina State University at Raleigh

Jaidev Patwardhan, North Carolina State University at Raleigh

pp. 0059

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An Instruction Set and Microarchitecture for Instruction Level Distributed Processing (Abstract)

Ho-Seop Kim, University of Wisconsin at Madison

James E. Smith, University of Wisconsin at Madison

pp. 0071

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Session 3: Safety and Reliability

Transient-Fault Recovery Using Simultaneous Multithreading (Abstract)

T. N. Vijaykumar, Purdue University

Irith Pomeranz, Purdue University

Karl Cheng, Purdue University

pp. 0087

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Detailed Design and Evaluation of Redundant Multithreading Alternatives (Abstract)

Shubhendu S. Mukherjee

Michael Kontz

Steven K. Reinhardt

pp. 0099

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ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors (Abstract)

Milos Prvulovic, University of Illinois at Urbana-Champaign

Josep Torrellas, University of Illinois at Urbana-Champaign

Zheng Zhang, Hewlett-Packard Laboratories (currently employed by Microsoft Research Asia)

pp. 0111

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SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery (Abstract)

Daniel J. Sorin, University of Wisconsin at Madison

Milo M.K. Martin, University of Wisconsin at Madison

Mark D. Hill, University of Wisconsin at Madison

David A. Wood, University of Wisconsin at Madison

pp. 0123

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Session 4: Power Aware Architecture

Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines (Abstract)

Seongmoo Heo, Massachusetts Institute of Technology

Kenneth Barr, Massachusetts Institute of Technology

Mark Hampton, Massachusetts Institute of Technology

Krste Asanovic, Massachusetts Institute of Technology

pp. 0137

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Drowsy Caches: Simple Techniques for Reducing Leakage Power (Abstract)

Krisztián Flautner, ARM Ltd

Nam Sung Kim, University of Michigan

Steve Martin, University of Michigan

David Blaauw, University of Michigan

Trevor Mudge, University of Michigan

pp. 0148

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Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors (Abstract)

Anoop Iyer

Diana Marculescu

pp. 0158

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Session 5: Memory Systems

Using a User-Level Memory Thread for Correlation Prefetching (Abstract)

Yan Solihin, University of Illinois at Urbana-Champaign

Josep Torrellas, University of Illinois at Urbana-Champaign

Jaejin Lee, Michigan State University

pp. 0171

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Avoiding Initialization Misses to the Heap (Abstract)

Jarrod A. Lewis, University of Wisconsin at Madison

Mikko H. Lipasti, University of Wisconsin at Madison

Bryan Black, Intel Corporation

pp. 0183

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Going the Distance for TLB Prefetching: An Application-Driven Study (Abstract)

Gokul B. Kandiraju, Pennsylvania State University

Anand Sivasubramaniam, Pennsylvania State University

pp. 0195

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Session 6: Dynamic Optimization

Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior (Abstract)

Zhigang Hu, Princeton University

Margaret Martonosi, Princeton University

Stefanos Kaxiras, Communication Systems and Software

pp. 0209

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Implementing Optimizations at Decode Time (Abstract)

Ilhyun Kim, University of Wisconsin at Madison

Mikko H. Lipasti, University of Wisconsin at Madison

pp. 0221

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Managing Multi-Configuration Hardware via Dynamic Working Set Analysis (Abstract)

Ashutosh S. Dhodapkar, University of Wisconsin at Madison

James E. Smith, University of Wisconsin at Madison

pp. 0233

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Session 7: Data and Storage Networks

Queue Pair IP: A Hybrid Architecture for System Area Networks (Abstract)

Philip Buonadonna, University of California at Berkeley and Intel Corporation

David E. Culler, University of California at Berkeley and Intel Corporation

pp. 0247

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Experiences with VI Communication for Database Storage (Abstract)

Yuanyuan Zhou, PrincetonUniversity

Kai Li, PrincetonUniversity

Angelos Bilas, Universityof Toronto

Suresh Jagannathan, Emphora Inc.

Cezary Dubnicki, Emphora Inc.

James F. Philbin, Emphora Inc.

pp. 0257

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Session 8: Vector Architectures

Speculative Dynamic Vectorization (Abstract)

Alex Pajuelo, Universitat Politecnica de Catalunya

Antonio Gonzalez, Universitat Politecnica de Catalunya

Mateo Valero, Universitat Politecnica de Catalunya

pp. 0271

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Tarantula: A Vector Extension to the Alpha Architecture (Abstract)

Roger Espasa, Universitat Polit?cnica de Catalunya

Federico Ardanaz, Universitat Polit?cnica de Catalunya

Julio Gago, Universitat Polit?cnica de Catalunya

Roger Gramunt, Universitat Polit?cnica de Catalunya

Isaac Hernandez, Universitat Polit?cnica de Catalunya

Toni Juan, Universitat Polit?cnica de Catalunya

Joel Emer, Compaq Computer Corporation

Stephen Felix, Compaq Computer Corporation

Geoff Lowney, Compaq Computer Corporation

Matthew Mattina, Compaq Computer Corporation

André Seznec, Compaq Computer Corporation

pp. 0281

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Session 9: Supporting Deep Speculation

Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor (Abstract)

André Seznec, IRISA/INRIA

Stephen Felix, Intel Inc.

Venkata Krishnan, StarGen, Inc.

Yiannakis Sazeides, University of Cyprus

pp. 0295

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Difficult-Path Branch Prediction Using Subordinate Microthreads (Abstract)

Robert S. Chappell, University of Michigan

Francis Tseng, University of Texas at Austin

Yale N. Patt, University of Texas at Austin

Adi Yoaz, Intel Corporation

pp. 0307

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A Scalable Instruction Queue Design Using Dependence Chains (Abstract)

Steven E. Raasch, University of Michigan

Nathan L. Binkert, University of Michigan

Steven K. Reinhardt, University of Michigan

pp. 0318

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Author Index (PDF)

pp. 0331