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29th Annual International Symposium on Computer Architecture (ISCA'02)
Anchorage, Alaska
May 25-May 29
ISBN: 0-7695-1605-X
Table of Contents
Session 1: Processor Pipelines
A. Hartstein, IBM -T.J.Watson Research Center
Thomas R. Puzak, IBM -T.J.Watson Research Center
pp. 0007
M. S. Hrishikesh, University of Texas at Austin
Doug Burger, University of Texas at Austin
Stephen W. Keckler, University of Texas at Austin
Premkishore Shivakumar, University of Texas at Austin
Norman P. Jouppi, Compaq Computer Corporation
Keith I. Farkas, Compaq Computer Corporation
pp. 0014
Session 2: Processor Scheduling
Brian Fields, University of Wisconsin at Madison
Rastislav Bodik, University of Wisconsin at Madison
Mark D. Hill, University of Wisconsin at Madison
pp. 0047
Alvin R. Lebeck, Duke University
Tong Li, Duke University
Eric Rotenberg, Duke University
Jinson Koppanalil, North Carolina State University at Raleigh
Jaidev Patwardhan, North Carolina State University at Raleigh
pp. 0059
Session 3: Safety and Reliability
Milos Prvulovic, University of Illinois at Urbana-Champaign
Josep Torrellas, University of Illinois at Urbana-Champaign
Zheng Zhang, Hewlett-Packard Laboratories (currently employed by Microsoft Research Asia)
pp. 0111
Daniel J. Sorin, University of Wisconsin at Madison
Milo M.K. Martin, University of Wisconsin at Madison
Mark D. Hill, University of Wisconsin at Madison
David A. Wood, University of Wisconsin at Madison
pp. 0123
Session 4: Power Aware Architecture
Seongmoo Heo, Massachusetts Institute of Technology
Kenneth Barr, Massachusetts Institute of Technology
Mark Hampton, Massachusetts Institute of Technology
Krste Asanovic, Massachusetts Institute of Technology
pp. 0137
Nam Sung Kim, University of Michigan
Steve Martin, University of Michigan
David Blaauw, University of Michigan
Trevor Mudge, University of Michigan
pp. 0148
Session 5: Memory Systems
Yan Solihin, University of Illinois at Urbana-Champaign
Josep Torrellas, University of Illinois at Urbana-Champaign
Jaejin Lee, Michigan State University
pp. 0171
Jarrod A. Lewis, University of Wisconsin at Madison
Mikko H. Lipasti, University of Wisconsin at Madison
Bryan Black, Intel Corporation
pp. 0183
Session 6: Dynamic Optimization
Ilhyun Kim, University of Wisconsin at Madison
Mikko H. Lipasti, University of Wisconsin at Madison
pp. 0221
Session 7: Data and Storage Networks
Philip Buonadonna, University of California at Berkeley and Intel Corporation
David E. Culler, University of California at Berkeley and Intel Corporation
pp. 0247
Yuanyuan Zhou, PrincetonUniversity
Kai Li, PrincetonUniversity
Angelos Bilas, Universityof Toronto
Suresh Jagannathan, Emphora Inc.
Cezary Dubnicki, Emphora Inc.
James F. Philbin, Emphora Inc.
pp. 0257
Session 8: Vector Architectures
Alex Pajuelo, Universitat Politecnica de Catalunya
Antonio Gonzalez, Universitat Politecnica de Catalunya
Mateo Valero, Universitat Politecnica de Catalunya
pp. 0271
Roger Espasa, Universitat Polit?cnica de Catalunya
Federico Ardanaz, Universitat Polit?cnica de Catalunya
Julio Gago, Universitat Polit?cnica de Catalunya
Roger Gramunt, Universitat Polit?cnica de Catalunya
Isaac Hernandez, Universitat Polit?cnica de Catalunya
Toni Juan, Universitat Polit?cnica de Catalunya
Joel Emer, Compaq Computer Corporation
Stephen Felix, Compaq Computer Corporation
Geoff Lowney, Compaq Computer Corporation
Matthew Mattina, Compaq Computer Corporation
André Seznec, Compaq Computer Corporation
pp. 0281
Session 9: Supporting Deep Speculation
Robert S. Chappell, University of Michigan
Francis Tseng, University of Texas at Austin
Yale N. Patt, University of Texas at Austin
Adi Yoaz, Intel Corporation
pp. 0307
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