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2000
27th Annual International Symposium on Computer Architecture (ISCA '00)
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27th Annual International Symposium on Computer Architecture (ISCA '00)
Vancouver, British Columbia, Canada
June 12-June 14
ISBN: 1-58113-232-8
Table of Contents
Session 1: Using Threads
A Scalable Approach to Thread-Level Speculation
(Abstract)
Antonia Zhai
Todd C. Mowry
Christopher B. Colohan
J. Greggory Steffan
pp. 1
ABSTRACT
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Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors
(Abstract)
Jos? F. Mart?nez
Josep Torrellas
Marcelo Cintra
pp. 13
ABSTRACT
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Transient Fault Detection via Simultaneous Multithreading
(Abstract)
Shubhendu S. Mukherjee
Steven K. Reinhardt
pp. 25
ABSTRACT
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Session 2a: Exploiting Traces
Trace Preconstruction
(Abstract)
James E. Smith
Quinn Jacobson
pp. 37
ABSTRACT
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Completion Time Multiple Branch Prediction for Enhancing Trace Cache Performance
(Abstract)
John Paul Shen
Bryan Black
Ryan Rakvic
pp. 47
ABSTRACT
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A Hardware Mechanism for Dynamic Extraction and Relayout of Pprogram Hot Spots
(Abstract)
Andrew R. Trick
Ronald D. Barnes
Wen-mei W. Hmu
Erik M. Nystrom
Matthew C. Merten
pp. 59
ABSTRACT
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Session 2b: Modeling Performance and Power
HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs
(Abstract)
Matthew Farrens
Frederic T. Chong
Mark Oskin
pp. 71
ABSTRACT
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Wattch: A Framework for Architectural-Level Power Analysis and Optimizations
(Abstract)
Margaret Martonosi
Vivek Tiwari
David Brooks
pp. 83
ABSTRACT
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Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower
(Abstract)
H. S. Kim
M. J. Irwin
M. Kandemir
W. Ye
N. Vijaykrishnan
pp. 95
ABSTRACT
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Session 3: Memory Hierarchy Improvements
A Fully Associative Software-Managed Cache Design
(Abstract)
Steven K. Reinhardt
Erik G. Hallnor
pp. 107
ABSTRACT
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Recency-Based TLB Preloading
(Abstract)
Per Stenstr?
Fredrik Dahlgren
Ashley Saulsbury
pp. 117
ABSTRACT
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Memory Access Scheduling
(Abstract)
John D. Owens
Peter Mattson
Ujval J. Kapasi
William J. Dally
Scott Rixner
pp. 128
ABSTRACT
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Session 4: Multiprocessors
Selective, Accurate, and Timely Self-Invalidation Using Last-Touch Prediction
(Abstract)
Babak Falsafi
An-Chow Lai
pp. 139
ABSTRACT
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An Embedded DRAM Architecture for Large-Scale Spatial-Lattice Computations
(Abstract)
Norman Margolus
pp. 149
ABSTRACT
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Smart Memories: A Modular Reconfigurable Architecture
(Abstract)
Mark Horowitz
Nuwan Jayasena
Ron Ho
Tim Paaske
William J. Dally
Ken Mai
pp. 161
ABSTRACT
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Session 5a: Analysis of Workloads and Systems
Understanding the Backward Slices of Performance Degrading Instructions
(Abstract)
Gurindar S. Sohi
Craig B. Zilles
pp. 172
ABSTRACT
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On the Value Locality of Store Instructions
(Abstract)
Mikko H. Lipasti
Kevin M. Lepak
pp. 182
ABSTRACT
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Performance Analysis of the Alpha 21264-Based Compaq ES40 System
(Abstract)
R. E. Kessler
Zarka Cvetanovic
pp. 192
ABSTRACT
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Session 5b: Customizable Systems
Lx: A Technology Platform for Customizable VLIW Embedded Processing
(Abstract)
Joseph A. Fisher
Fred Homewood
Geoffrey Brown
Giuseppe Desoli
Paolo Faraboschi
pp. 203
ABSTRACT
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Reconfigurable Caches and Their Application to Media Processing
(Abstract)
Norman P. Jouppi
Sarita Adve
Parthasarathy Ranganathan
pp. 214
ABSTRACT
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CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit
(Abstract)
Andreas Moshovos
Prithviraj Banerjee
Scott Hauck
Zhi Alex Ye
pp. 225
ABSTRACT
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Session 6: Circuit Considerations
Circuits for Wide-Window Superscalar Processors
(Abstract)
Rahul Sami
Bradley C. Kuszmaul
Gabriel H. Loh
Dana S. Henry
pp. 236
ABSTRACT
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Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures
(Abstract)
M. S. Hrishikesh
Stephen W. Keckler
Doug Burger
Vikas Agarwal
pp. 248
ABSTRACT
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Session 7: Extracting Parallelism
Vector Instruction Set Support for Conditional Operations
(Abstract)
Rabin Sugumar
Greg Faanes
J. E. Smith
pp. 260
ABSTRACT
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Instruction Path Coprocessors
(Abstract)
John Paul Shen
Yuan Chou
pp. 270
ABSTRACT
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Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing
(Abstract)
Kourosh Gharachorloo
Andreas Nowatzyk
Robert McNamara
Robert Stets
Scott Smith
Shaz Qadeer
Barton Sano
Ben Verghese
Luiz Andr? Barroso
pp. 282
ABSTRACT
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Session 8: Microarchitecture Innovations
Allowing for ILP in an Embedded Java Processor
(Abstract)
Lizy Kurian John
Deependra Talla
Ramesh Radhakrishnan
pp. 294
ABSTRACT
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Early Load Address Resolution via Register Tracking
(Abstract)
Adi Yoaz
Maxim Kalaev
Ronny Ronen
Stephan Jourdan
Freddy Gabbay
Michael Bekerman
pp. 306
ABSTRACT
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Multiple-Banked Register File Architectures
(Abstract)
Mateo Valero
Antonio Gonz?lez
Nigel P. Topham
Jos?-Lorenzo Cruz
pp. 316
ABSTRACT
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