CSDL - Proceedings I

Program Chair's Message (PDF)

pp. x

Conference Organization (PDF)

pp. xi

Referees (PDF)

pp. xii

Session 2: Machine Measurement

Memory System Characterization of Commercial Workloads (Abstract)

pp. 0003

PDF

Performance Characterization of a Quad Pentium Pro SMP using OLTP Workloads (Abstract)

Y. He

pp. 0015

PDF

Execution Characteristics of Desktop Applications on Windows NT (Abstract)

D. Lee

J. Baer

pp. 0027

PDF

An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors (Abstract)

J. Lo

H. Levy

pp. 0039

PDF

Session 3A: Program Behavior

An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work (Abstract)

M. Evers

S. Patel

R. Chappell

Y. Patt

pp. 0052

PDF

Branch Prediction based on Universal Data Compression Algorithms (Abstract)

pp. 0062

PDF

Modeling Program Predictability (Abstract)

Y. Sazeides

J. Smith

pp. 0073

PDF

Session 3B: Graphics and IO

Multi-Level Texture Caching for 3D Graphics Hardware (Abstract)

M. Cox

N. Bhandari

M. Shantz

pp. 0086

PDF

Switcherland: A QoS Communication Architecture for Workstation Clusters (Abstract)

H. Eberle

E. Oertli

pp. 0098

PDF

Declustered Disk Array Architectures with Optimal and Near-Optimal Parallelism (Abstract)

pp. 0109

PDF

Session 4: Speculation

Confidence Estimation for Speculation Control (Abstract)

pp. 0122

PDF

Pipeline Gating: Speculation Control for Energy Reduction (Abstract)

pp. 0132

PDF

Memory Dependence Prediction using Store Sets (Abstract)

G. Chrysos

J. Emer

pp. 0142

PDF

Session 5A: Prediction Techniques

Dynamic History-Length Fitting: A Third Level of Adaptivity for Branch Prediction (Abstract)

T. Juan

S. Sanjeevan

J. Navarro

pp. 0155

PDF

Accurate Indirect Branch Prediction (Abstract)

K. Driesen

U. Hölzle

pp. 0167

PDF

Using Prediction to Accelerate Coherence Protocols (Abstract)

S. Mukherjee

M. Hill

pp. 0179

PDF

Session 5B: Memory Management

Active Pages: A Computation Model for Intelligent Memory (Abstract)

pp. 0192

PDF

Increasing TLB Reach using Superpages Backed by Shadow Memory (Abstract)

pp. 0204

PDF

Options for Dynamic Address Translation in COMAs (Abstract)

X. Qiu

M. Dubois

pp. 0214

PDF

Session 6: Predication and Multipath Execution

Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture (Abstract)

D. August

D. Connors

S. Mahlke

J. Sias

pp. 0227

PDF

Threaded Multiple Path Execution (Abstract)

pp. 0238

PDF

Selective Eager Execution on the PolyPath Architecture (Abstract)

pp. 0250

PDF

Session 8A: Processor Microarchitecture

Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing (Abstract)

F. Gabbay

A. Mendelson

pp. 0272

PDF

The Effect of Instruction Fetch Bandwidth on Value Prediction (Abstract)

S. Patel

M. Evers

Y. Patt

pp. 0262

PDF

Dynamic IPC/Clock Rate Optimization (Abstract)

D. Albonesi

pp. 0282

PDF

Performance Modeling and Code Partitioning for the DS Architecture (Abstract)

Y. Zhang

G. Adams Iii

pp. 0293

PDF

Session 8B: Parallel Machines

Exploiting Fine-Grain Thread Level Parallelism on the MIT Multi-ALU Processor (Abstract)

W. Lee

pp. 0306

PDF

Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance (Abstract)

G. Abandah

E. Davidson

pp. 0318

PDF

Design Choices in the SHRIMP System: An Empirical Study (Abstract)

Y. Chen

K. Li

pp. 0330

PDF

Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors (Abstract)

pp. 0342

PDF

Session 9: Caches and Memory Systems

Exploiting Spatial Locality in Data Caches using Spatial Footprints (Abstract)

S. Kumar

C. Wilkerson

pp. 0357

PDF

Low Load Latency through Sum-Addressed Memory (SAM) (Abstract)

pp. 0369

PDF

Analytic Evaluation of Shared-Memory Systems with ILP Processors (Abstract)

D. Sorin

V. Pai

S. Adve

M. Vernon

D. Wood

pp. 0380

PDF

Index of Authors (Abstract)

pp. 0393

PDF