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ISCA
1995
22nd Annual International Symposium on Computer Architecture (ISCA'95)
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Refworks Procite/RefMan
22nd Annual International Symposium on Computer Architecture (ISCA'95)
S. Margherita Ligure, Italy
June 22-June 24
ISBN: 0-89791-698-0
Table of Contents
Session 1: Multiprocessors and Applications
The MIT Alewife Machine: Architecture and Performance
(Abstract)
John Kubiatowicz
Kenneth Mackenzie
Kirk L. Johnson
Ricardo Bianchini
Beng-Hong Lim
David Chaiken
David Kranz
Donald Yeung
Anant Agarwal
pp. 2
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The EM-X Parallel Computer: Architecture and Basic Performance
(Abstract)
Hayato Yamana
Hirohumi Sakane
Mitsuhisa Sato
Shuichi Sakai
Yoshinori Yamaguchi
Yuetsu Kodama
pp. 14
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The SPLASH-2 Programs: Characterization and Methodological Considerations
(Abstract)
Jaswinder Pal Singh
Anoop Gupta
Moriyoshi Ohara
Evan Torrie
Steven Cameron Woo
pp. 24
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Session 2A: Cache Coherence
Efficient Strategies for Software-Only Protocols in Shared-Memory Multiprocessors
(Abstract)
Per Stenstr?
H?kan Grahn
pp. 38
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Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
(Abstract)
David A. Wood
Alvin R. Lebeck
pp. 48
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Boosting the Performance of Hybrid Snooping Cache Protocols
(Abstract)
Fredrik Dahlgren
pp. 60
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Session 2B: Interconnect Technology and I/O
S-Connect: from Networks of Workstations to Supercomputer Performance
(Abstract)
Michael C. Browne
Michael Parkin
Edmund J. Kelly
Andreas G. Nowatzyk
pp. 71
ABSTRACT
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Destage Algorithms for Disk Arrays with Non-Volatile Caches
(Abstract)
Quinn Jacobson
Anujan Varma
pp. 83
ABSTRACT
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Evaluating Multi-Port Frame Buffer Designs for a Mesh-Connected Multicomputer
(Abstract)
Kai Li
Patrick Hanrahan
Bin Wei
Douglas Clark
Edward W. Felten
Gordon Stoll
pp. 96
ABSTRACT
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Are Crossbars Really Dead?: The Case for Optical Multiprocessor Interconnect Systems
(Abstract)
Paul R. Prucnal
Andreas G. Nowatzyk
pp. 106
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Session 3: Instruction Level Parallelism
Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor
(Abstract)
Pascal Sainrat
Daniel Litaize
St?phan Jourdan
pp. 117
ABSTRACT
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Unconstrained Speculative Execution with Predicated State Buffering
(Abstract)
Masao Nakaya
Tetsuya Hara
Chikako Nakanishi
Hideki Ando
pp. 126
ABSTRACT
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A Comparison of Full and Partial Predicated Execution Support for ILP Processors
(Abstract)
James E. McCormick
Richard E. Hank
Wen-Mei W. Hwu
David I. August
Scott A. Mahlke
pp. 138
ABSTRACT
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Session 4A: New Microarchitectures
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor
(Abstract)
M. Ramaswami
M. Shebanow
N. Patkar
T. Maruyama
V. Thirumalaiswamy
A. Essen
A. Ike
A. Krishnamoorthy
D. Tovey
M. Simone
pp. 151
ABSTRACT
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Performance Evaluation of the PowerPC 620 Microarchitecture
(Abstract)
John Paul Shen
Christopher Nelson
Trung A. Diep
pp. 163
ABSTRACT
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Session 4B: Managing Memory Hierarchies
Reducing TLB and Memory Overhead Using Online Superpage Promotion
(Abstract)
Anna R. Karlin
Wayne H. Ohlrich
Brian N. Bershad
Theodore H. Romer
pp. 176
ABSTRACT
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Speeding Up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching
(Abstract)
Josep Torrellas
Zheng Zhang
pp. 188
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Session 5A: Interconnection Network Routing
An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA
(Abstract)
Timothy Mark Pinkston
K. V. Anjan
pp. 201
ABSTRACT
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Analysis and Implementation of Hybrid Switching
(Abstract)
Stuart W. Daniel
Kang G. Shin
pp. 211
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Configurable Flow Control Mechanisms for Fault-Tolerant Routing
(Abstract)
Jose Duato
Sudhakar Yalamanchili
Binh Vien Dao
pp. 220
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NIFDY: A Low Overhead, High Throughput Network Interface
(Abstract)
Seth Copen Goldstein
Timothy Callahan
pp. 230
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Session 5B: Novel Memory Access Mechanisms
Vector Multiprocessors with Arbitrated Memory Access
(Abstract)
Mateo Valero
Tom? Lang
Eduard Ayguad?
Montse Peiron
pp. 243
ABSTRACT
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Design of Cache Memories for Multi-Threaded Dataflow Architecture
(Abstract)
Phenil Patadia
Ponnarasu Shanmugam
A. R. Hurson
Elizabeth Abraham
Krishna M. Kavi
pp. 253
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Skewed Associativity Enhances Performance Predictability
(Abstract)
Andr? Seznec
Fran?ois Bodin
pp. 265
ABSTRACT
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Session 6: Branch Prediction
A Comparative Analysis of Schemes for Correlated Branch Prediction
(Abstract)
Michael D. Smith
Nicolas Gloy
Cliff Young
pp. 276
ABSTRACT
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Next Cache Line and Set Prediction
(Abstract)
Dirk Grunwald
Brad Calder
pp. 287
ABSTRACT
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Session 7A: System Evaluation
A Comparison of Architectural Support for Messaging in the TMC CM-5 and the Cray T3D
(Abstract)
Andrew A. Chien
Vijay Karamcheti
pp. 298
ABSTRACT
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Optimizing Memory System Performance for Communication in Parallel Computers
(Abstract)
T. Gross
T. Stricker
pp. 308
ABSTRACT
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Empirical Evaluation of the CRAY-T3D: A Compiler Perspective
(Abstract)
Katherine Yelick
Arvind Krishnamurthy
Steve G. Steinberg
David E. Culler
Remzi H. Arpaci
pp. 320
ABSTRACT
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Session 7B: Instruction Fetching
Optimization of Instruction Fetch Mechanisms for High Issue Rates
(Abstract)
Kishore N. Menezes
Patrick M. Mills
Burzin A. Patel
Thomas M. Conte
pp. 333
ABSTRACT
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Instruction Fetching: Coping with Code Bloat
(Abstract)
Joel Emer
Stuart Sechrest
Trevor Mudge
David Nagle
Richard Uhlig
pp. 345
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Instruction Cache Fetch Policies for Speculative Execution
(Abstract)
Jean-Loup Baer
Brad Calder
Dirk Grunwald
Dennis Lee
pp. 357
ABSTRACT
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Session 8: Caches
Streamlining Data Cache Access with Fast Address Calculation
(Abstract)
Gurindar S. Sohi
Dionisios N. Pnevmatikatos
Todd M. Austin
pp. 369
ABSTRACT
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CAT--- Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches
(Abstract)
Qing Yang
Tong Sun
Hong Wang
pp. 381
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Session 9: Processor Architecture
Simultaneous Multithreading: Maximizing On-Chip Parallelism
(Abstract)
Henry M. Levy
Susan J. Eggers
Dean M. Tullsen
pp. 392
ABSTRACT
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Architecture Validation for Processors
(Abstract)
Mark A. Horowitz
C. Han Yang
David L. Dill
Richard C. Ho
pp. 404
ABSTRACT
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Multiscalar Processors
(Abstract)
Scott E. Breach
T. N. Vijaykumar
Gurindar S. Sohi
pp. 414
ABSTRACT
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