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18th International Parallel and Distributed Processing Symposium (IPDPS'04) - Workshop 3
A Dynamically-Reconfigurable Image Recognition Processor
Santa Fe, New Mexico
April 26-April 30
ISBN: 0-7695-2132-0
ASCII Text
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Kazuyuki Maruo, Masayoshi Ichikawa, Naoto Miyamoto, Leo Karnan, Takahiro Yamaguchi, Koji Kotani, Tadahiro Ohmi, "A Dynamically-Reconfigurable Image Recognition Processor," Parallel and Distributed Processing Symposium, International, vol. 4, pp. 151b, 18th International Parallel and Distributed Processing Symposium (IPDPS'04) - Workshop 3, 2004.
 
 
BibTex
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@article{ 10.1109/IPDPS.2004.1303139,
author = {Kazuyuki Maruo and Masayoshi Ichikawa and Naoto Miyamoto and Leo Karnan and Takahiro Yamaguchi and Koji Kotani and Tadahiro Ohmi},
title = {A Dynamically-Reconfigurable Image Recognition Processor},
journal ={Parallel and Distributed Processing Symposium, International},
volume = {4},
year = {2004},
isbn = {0-7695-2132-0},
pages = {151b},
doi = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2004.1303139},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel and Distributed Processing Symposium, International
TI - A Dynamically-Reconfigurable Image Recognition Processor
SN - 0-7695-2132-0
SP
EP
A1 - Kazuyuki Maruo,
A1 - Masayoshi Ichikawa,
A1 - Naoto Miyamoto,
A1 - Leo Karnan,
A1 - Takahiro Yamaguchi,
A1 - Koji Kotani,
A1 - Tadahiro Ohmi,
PY - 2004
KW - null
VL - 4
JA - Parallel and Distributed Processing Symposium, International
ER -
 
Kazuyuki Maruo, Advantest Laboratories Ltd.
Masayoshi Ichikawa, Advantest Corporation
Naoto Miyamoto, Tohoku University
Leo Karnan, Tohoku University
Takahiro Yamaguchi, Advantest Laboratories Ltd.
Koji Kotani, Tohoku University
Tadahiro Ohmi, Tohoku University
This paper introduces a new image recognition processor using a run-time reconfiguration (RTR) technology. A phase impulse response function (PIRF) is employed as an application for evaluating the performance of RTR architecture. By utilizing the RTR architecture effectively, a complicated image processing application such as PIRF can be implemented on a single processor. To achieve this, a dynamically-reconfigurable arithmetic logic unit (DRALU) is proposed. Simulation results show that our proposed processor using DRALU can execute the PIRF within 30 msec.
Citation:
Kazuyuki Maruo, Masayoshi Ichikawa, Naoto Miyamoto, Leo Karnan, Takahiro Yamaguchi, Koji Kotani, Tadahiro Ohmi, "A Dynamically-Reconfigurable Image Recognition Processor," ipdps, vol. 4, pp.151b, 18th International Parallel and Distributed Processing Symposium (IPDPS'04) - Workshop 3, 2004
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