CSDL - Proceedings I

Conference Organization (PDF)

pp. xiii

TTTC Information (PDF)

pp. 271

Session 1: Hardware Fault Tolerance

An Architecture for Self-Healing Digital Systems (Abstract)

P. K. Lala, University of Arkansas

B. Kiran Kumar, University of Arkansas

pp. 3

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Coding Scheme for Low Energy Consumption Fault-Tolerant Bus (Abstract)

D. Rossi, University of Bologna

V. E. S. van Dijk, Philips Research Laboratories

R. P. Kleihorst, Philips Research Laboratories

A. H. Nieuwland, Philips Research Laboratories

C. Metra, University of Bologna

pp. 8

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Survivable Discrete Circuits Design (Abstract)

A. Matrosova, Tomsk State University

V. Andreeva, Tomsk State University

Yu. Sedov, Tomsk State University

pp. 13

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Session 2: Hardware-Software Design and Validation of Fault Tolerant Systems

Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods (Abstract)

Astrit Ademaj, Vienna University of Technology

Petr Grillinger, University of West Bohemia

Pavel Herout, University of West Bohemia

Jan Hlavicka, Czech Technical University

pp. 21

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Automated Synthesis of SEU Tolerant Architectures from OO Descriptions (Abstract)

S. Chiusano, Politechnico di Torino

S. DiI Carlo, Politechnico di Torino

P. Prinetto, Politechnico di Torino

pp. 26

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A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems (Abstract)

C. Bolchini, Politecnico di Milano

L. Pomante, Politecnico di Milano

F. Salice, Politecnico di Milano

D. Sciuto, Politecnico di Milano

pp. 32

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Session 3: Self Checking Circuits

A New Self-Checking Code-Disjoint Carry-Skip Adder (Abstract)

D. Marienfeld, University of Potsdam

E. S. Sogomonyan, University of Potsdam

V. Ocheretnij, University of Potsdam

M. Gössel, University of Potsdam

pp. 39

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Sequential Circuits Applicable for Detecting Different Types of Faults (Abstract)

I. Levin, Tel-Aviv University

V. Sinelnikov, Tel-Aviv University

M. Karpovsky, Boston University

S. Ostanin, Tel-Aviv University

pp. 44

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Session 4: Concurrent Error Detection I

A High Speed Encoder for Recursive Systematic Convolutive Codes (Abstract)

A. M?sir, LICM/CLOES, SUPELEC & University of Metz

F. Monteiro, LICM/CLOES, SUPELEC & University of Metz

A. Dandache, LICM/CLOES, SUPELEC & University of Metz

B. Lepley, LICM/CLOES, SUPELEC & University of Metz

pp. 51

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A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing (Abstract)

Y. Tsiatouhas, ISD S.A.

A. Arapoyanni, University of Athens

D. Nikolos, University of Patras

Th. Haniotakis, Southern Illinois University

pp. 56

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Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems (Abstract)

Huy Nguyen, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

pp. 61

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Session 5: Concurrent Error Detection II

On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check (Abstract)

M. Pflanz, IBM Deutschland Entwicklung GmbH

K. Walther, Brandenburg Technical University of Cottbus

C. Galke, Brandenburg Technical University of Cottbus

H. T. Vierhaus, Brandenburg Technical University of Cottbus

pp. 69

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On-Line Monitor Design of Finite-State Machines (Abstract)

Feng Gao, University of Michigan

John P. Hayes, University of Michigan

pp. 74

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A Statistical Sampler for a New On-line Analog Test Method (Abstract)

M. Negreiros, Universidade Federal do Rio Grande do Sul

L. Carro, Universidade Federal do Rio Grande do Sul

A. A. Susin, Universidade Federal do Rio Grande do Sul

pp. 79

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Session 6: Analog and Mixed Signal Testing and Reliability

A ΣΔ A/D Converter Insensitive to SEU Effects (PDF)

Fernando Paixão Cortes, Universidade Federal do Rio Grande do Sul

Luigi Carro, Universidade Federal do Rio Grande do Sul

Alessandro Girardi, Universidade Federal do Rio Grande do Sul

Altamiro Suzim, Universidade Federal do Rio Grande do Sul

A BICS for CMOS Opamps by Monitoring the Supply Current Peak (Abstract)

J. Font, Universitat Illes Balears

J. Ginard, Universitat Illes Balears

E. Isern, Universitat Illes Balears

M. Roca, Universitat Illes Balears

J. Segura, Universitat Illes Balears

E. García, Universitat Illes Balears

pp. 94

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Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours (Abstract)

R. Rodríguez-Montañés, Universitat Polit?cnica de Catalunya

D. Muñoz, Universitat Polit?cnica de Catalunya

L. Balado, Universitat Polit?cnica de Catalunya

J. Figueras, Universitat Polit?cnica de Catalunya

pp. 99

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Session 7: Fault Injection Techniques and Results

Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study (Abstract)

R. Leveugle, TIMA Laboratory

K. Hadjiat, TIMA Laboratory

pp. 107

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Analysis of SEU Effects in a Pipelined Processor (Abstract)

M. Rebaudengo, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

M. Violante, Politecnico di Torino

pp. 112

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Bit Flip Injection in Processor-Based Architectures: A Case Study (Abstract)

G. C. Cardarilli, University of Rome "Tor Vergata"

F. Kaddour, TIMA laboratory

A. Leandri, University of Rome "Tor Vergata"

M. Ottavi, University of Rome "Tor Vergata"

S. Pontarelli, University of Rome "Tor Vergata"

R. Velazco, TIMA laboratory

pp. 117

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Session 8: BIST Techniques I

BIST-Based Delay-Fault Testing in FPGAs (Abstract)

Miron Abramovici, Agere Systems

Charles Stroud, University of North Carolina at Charlotte

pp. 131

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Built-In-Self-Test of Analogue Circuits Using Optimised Fault Sets and Transient Response Testing (Abstract)

N. Axelos, University of Huddersfield

J. Watson, University of Huddersfield

D. Taylor, University of Huddersfield

A. Platts, University of Huddersfield

pp. 135

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A Low Power Pseudo-Random BIST Technique (Abstract)

Nadir Z. Basturkmen, University of Iowa

Sudhakar M. Reddy, University of Iowa

Irith Pomeranz, Purdue University

pp. 140

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Session 9: BIST Techniques II

Stop & Go BIST (Abstract)

Ilia Polian, Albert-Ludwigs-University

Bernd Becker, Albert-Ludwigs-University

pp. 147

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Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register (Abstract)

G. Dimitrakopoulos, University of Patras

D. Nikolos, University of Patras and Computer Technology Institute

D. Bakalis, University of Patras and Computer Technology Institute

pp. 152

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Built-in Generation of m -Sequences with Irreducible Characteristic Polynomials (Abstract)

Dimitri Kagaris, Southern Illinois University

pp. 158

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Session 10: Testing Issues

Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing (Abstract)

Manuel G. Gericota, ISEP

Gustavo R. Alves, ISEP

Miguel L. Silva, FEUP

José M. Ferreira, FEUP

pp. 165

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Checkers for RF Matching Networks on an Automatic Test Board (Abstract)

Giuseppe Di Gregorio, STMicroelectronics

Maria Grazia La Rosa, STMicroelectronics

Biagio Russo, STMicroelectronics

pp. 170

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Session 11: Posters

Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under Test (PDF)

Carlo Dallavalle, ST Microelectronics

pp. 177

On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures (PDF)

C. Galke, Brandenburg University of Technology Cottbus

M. Pflanz, IBM Deutschland Entwicklung GmbH

H. T. Vierhaus, Brandenburg University of Technology Cottbus

pp. 178

Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells (PDF)

Jose Miguel Vieira dos Santos, ISEP - DEE

pp. 179

Learning-Based On-Line Testing in Feedforward Neural Networks (Abstract)

Naotake Kamiura, Himeji Institute of Technology

Kazuharu Yamato, Hyogo University

Teijiro Isokawa, Himeji Institute of Technology

Nobuyuki Matsui, Himeji Institute of Technology

pp. 180

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On-Line Detection of Short Circuits in Digital Devices and Systems (PDF)

Adam Kristof, Silesian University of Technology in Gliwice

pp. 183

Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable Approach (PDF)

M. A. Naal, TIMA Laboratory

M. Rakotoar, TIMA Laboratory

E. Simeu, TIMA Laboratory

C. Aktouf, LCIS-ESISAR

pp. 184

Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment (PDF)

Petros Oikonomakos, University of Southampton

Mark Zwolinski, University of Southampton

pp. 185

Robust Data Compression for Analogue Test Outputs (PDF)

Aleksandra Rankov, Leeds Metropolitan University

Gaynor E. Taylor, Leeds Metropolitan University

John Webster, Leeds Metropolitan University

pp. 186

A New On-Line Robust Approach to Design Noise Immune Speech Recognition Systems (PDF)

F. Vargas, Catholic University - PUCRS

R. D. Fagundes, Catholic University - PUCRS

D. Barros Jr., Catholic University - PUCRS

pp. 187

Radiation Effects Facility RADEF (PDF)

Ari Virtanen, University of Jyv?skyl?

pp. 188

Sequential n -Detection Criteria: Keep It Simple! (PDF)

Ilia Polian, Albert-Ludwigs-University

Martin Keim, Mentor Graphics Corp.

Nicolai Mallig, Albert-Ludwigs-University

Bernd Becker, Albert-Ludwigs-University

pp. 189

On-line Testing of Embedded Systems Using Optical Probes: System Modeling and Probing Technology (PDF)

Chouki Aktouf, LCIS-INPG

Benoît Pannetier, LCIS-INPG

Pierre Lemaître- Auger, LCIS-INPG

Smail Tedjini, LCIS-INPG

pp. 191

An Off-Chip Sensor Circuit for On-Line Transient Current Testing (PDF)

B. Alorda, Université de les Illes Balears

A. Ivanov, University of British Columbia

J. Segura, Université de les Illes Balears

pp. 192

Analysis of the Equivalences and Dominances of Transient Faults at the RT Level (PDF)

Luis Berrojo, Alcatel Espacio

Isabel González, Alcatel Espacio

Luis Entrena, Universidad Carlos III de Madrid

Celia López, Universidad Carlos III de Madrid

Fulvio Corno, Polit?cnico di Torino

Matteo Sonza, Polit?cnico di Torino

Giovanni Squillero, Polit?cnico di Torino

pp. 193

Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller (PDF)

F. Lima, Federal University of Rio Grande do Sul

L. Carro, Federal University of Rio Grande do Sul

R. Velazco, TIMA Laboratory

R. Reis, Federal University of Rio Grande do Sul

pp. 194

Error Rate Estimation for a Flight Application Using the CEU Fault Injection Approach (PDF)

F. Kaddour, TIMA Laboratory

S. Rezgui, TIMA Laboratory

R. Velazco, TIMA Laboratory

S. Rodriguez, INTA

J. R. De Mingo, INTA

pp. 195

Session 12: Memory BIST Analysis and Application

Defect-Oriented Analysis of Memory BIST Tests (Abstract)

Alvin Jee, HPL, Inc.

pp. 201

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A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques (Abstract)

D. Appello, STMicroelectronics

A. Fudoli, STMicroelectronics

V. Tancorre, STMicroelectronics

F. Corno, Politecnico di Torino

M. Rebaudengo, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

pp. 206

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A Scan-Bist Environment for Testing Embedded Memories (Abstract)

F. Karimi, LTX Corporation

F. Lombardi, Northeastern University

pp. 211

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Session 13: Memory ECC and Soft Errors

Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories (Abstract)

D. Rossi, University of Bologna

C. Metra, University of Bologna

B. Riccò, University of Bologna

pp. 221

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High Speed 15 ns 4 Mbits SRAM for Space Application (Abstract)

Bernard Coloma, Atmel Corporation

Patrick Delaunay, Atmel Corporation

Olivier Husson, Atmel Corporation

pp. 226

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Session 14: High Reliability in Railway and Automotive Systems

The YATE Fail-Safe Interface: The User?s Point of View (Abstract)

D. Bied-Charreton, INRETS

D. Guillon, TECHNICATOME

B. Jacques, CSEE Transport

pp. 233

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Fault Tolerant Insertion and Verification: A Case Study (Abstract)

Alberto Manzone, Centro Ricerche FIAT

Diego De Costantini, Centro Ricerche FIAT

pp. 238

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Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems (Abstract)

Luca Schiano, University of Bologna

Cecilia Metra, University of Bologna

Diego Marino, Alstom Transport Spa

pp. 243

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Session 15: Embedded Memory Yield Enhancement

A Silicon-Based Yiel Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios (Abstract)

E. Rondey, Altis Semiconductor

Y. Tellier, Infineon Technologies

S. Borri, Infineon Technologies

pp. 251

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A March-Based Fault Location Algorithm for Static Random Access Memories (Abstract)

V. A. Vardanian, Virage Logic Int.

Y. Zorian, Virage Logic Int.

pp. 256

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A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories (Abstract)

Rei-Fu Huang, National Tsing Hua University

Jin-Fu Li, National Tsing Hua University

Jen-Chieh Yeh, National Tsing Hua University

Cheng-Wen Wu, National Tsing Hua University

pp. 262

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Author Index

Author Index (PDF)

pp. 269