• I
  • IOLTW
  • 2002
  • Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Advanced Search 
Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Isle of Bendor, France
July 08-July 10
ISBN: 0-7695-1641-6
Table of Contents
Introduction
Session 1: Hardware Fault Tolerance
D. Rossi, University of Bologna
V. E. S. van Dijk, Philips Research Laboratories
R. P. Kleihorst, Philips Research Laboratories
A. H. Nieuwland, Philips Research Laboratories
C. Metra, University of Bologna
pp. 8
A. Matrosova, Tomsk State University
V. Andreeva, Tomsk State University
Yu. Sedov, Tomsk State University
pp. 13
Session 2: Hardware-Software Design and Validation of Fault Tolerant Systems
Astrit Ademaj, Vienna University of Technology
Petr Grillinger, University of West Bohemia
Pavel Herout, University of West Bohemia
Jan Hlavicka, Czech Technical University
pp. 21
C. Bolchini, Politecnico di Milano
L. Pomante, Politecnico di Milano
F. Salice, Politecnico di Milano
D. Sciuto, Politecnico di Milano
pp. 32
Session 3: Self Checking Circuits
D. Marienfeld, University of Potsdam
E. S. Sogomonyan, University of Potsdam
V. Ocheretnij, University of Potsdam
M. Gössel, University of Potsdam
pp. 39
Session 4: Concurrent Error Detection I
A. M?sir, LICM/CLOES, SUPELEC & University of Metz
F. Monteiro, LICM/CLOES, SUPELEC & University of Metz
A. Dandache, LICM/CLOES, SUPELEC & University of Metz
B. Lepley, LICM/CLOES, SUPELEC & University of Metz
pp. 51
Session 5: Concurrent Error Detection II
M. Pflanz, IBM Deutschland Entwicklung GmbH
K. Walther, Brandenburg Technical University of Cottbus
C. Galke, Brandenburg Technical University of Cottbus
H. T. Vierhaus, Brandenburg Technical University of Cottbus
pp. 69
M. Negreiros, Universidade Federal do Rio Grande do Sul
L. Carro, Universidade Federal do Rio Grande do Sul
A. A. Susin, Universidade Federal do Rio Grande do Sul
pp. 79
Session 6: Analog and Mixed Signal Testing and Reliability
Fernando Paixão Cortes, Universidade Federal do Rio Grande do Sul
Luigi Carro, Universidade Federal do Rio Grande do Sul
Alessandro Girardi, Universidade Federal do Rio Grande do Sul
Altamiro Suzim, Universidade Federal do Rio Grande do Sul
J. Font, Universitat Illes Balears
J. Ginard, Universitat Illes Balears
E. Isern, Universitat Illes Balears
M. Roca, Universitat Illes Balears
J. Segura, Universitat Illes Balears
E. García, Universitat Illes Balears
pp. 94
R. Rodríguez-Montañés, Universitat Polit?cnica de Catalunya
D. Muñoz, Universitat Polit?cnica de Catalunya
L. Balado, Universitat Polit?cnica de Catalunya
J. Figueras, Universitat Polit?cnica de Catalunya
pp. 99
Session 7: Fault Injection Techniques and Results
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino
pp. 112
G. C. Cardarilli, University of Rome "Tor Vergata"
F. Kaddour, TIMA laboratory
A. Leandri, University of Rome "Tor Vergata"
M. Ottavi, University of Rome "Tor Vergata"
S. Pontarelli, University of Rome "Tor Vergata"
R. Velazco, TIMA laboratory
pp. 117
Session 8: BIST Techniques I
Miron Abramovici, Agere Systems
Charles Stroud, University of North Carolina at Charlotte
pp. 131
N. Axelos, University of Huddersfield
J. Watson, University of Huddersfield
D. Taylor, University of Huddersfield
A. Platts, University of Huddersfield
pp. 135
Session 9: BIST Techniques II
Stop & Go BIST (Abstract)
Ilia Polian, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
pp. 147
G. Dimitrakopoulos, University of Patras
D. Nikolos, University of Patras and Computer Technology Institute
D. Bakalis, University of Patras and Computer Technology Institute
pp. 152
Session 10: Testing Issues
Session 11: Posters
C. Galke, Brandenburg University of Technology Cottbus
M. Pflanz, IBM Deutschland Entwicklung GmbH
H. T. Vierhaus, Brandenburg University of Technology Cottbus
pp. 178
Naotake Kamiura, Himeji Institute of Technology
Kazuharu Yamato, Hyogo University
Teijiro Isokawa, Himeji Institute of Technology
Nobuyuki Matsui, Himeji Institute of Technology
pp. 180
Aleksandra Rankov, Leeds Metropolitan University
Gaynor E. Taylor, Leeds Metropolitan University
John Webster, Leeds Metropolitan University
pp. 186
F. Vargas, Catholic University - PUCRS
R. D. Fagundes, Catholic University - PUCRS
D. Barros Jr., Catholic University - PUCRS
pp. 187
Ari Virtanen, University of Jyv?skyl?
pp. 188
Ilia Polian, Albert-Ludwigs-University
Martin Keim, Mentor Graphics Corp.
Nicolai Mallig, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
pp. 189
B. Alorda, Université de les Illes Balears
A. Ivanov, University of British Columbia
J. Segura, Université de les Illes Balears
pp. 192
Luis Berrojo, Alcatel Espacio
Isabel González, Alcatel Espacio
Luis Entrena, Universidad Carlos III de Madrid
Celia López, Universidad Carlos III de Madrid
Fulvio Corno, Polit?cnico di Torino
Matteo Sonza, Polit?cnico di Torino
Giovanni Squillero, Polit?cnico di Torino
pp. 193
F. Lima, Federal University of Rio Grande do Sul
L. Carro, Federal University of Rio Grande do Sul
R. Velazco, TIMA Laboratory
R. Reis, Federal University of Rio Grande do Sul
pp. 194
Session 12: Memory BIST Analysis and Application
D. Appello, STMicroelectronics
A. Fudoli, STMicroelectronics
V. Tancorre, STMicroelectronics
F. Corno, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
pp. 206
Session 13: Memory ECC and Soft Errors
Session 14: High Reliability in Railway and Automotive Systems
Session 15: Embedded Memory Yield Enhancement
Rei-Fu Huang, National Tsing Hua University
Jin-Fu Li, National Tsing Hua University
Jen-Chieh Yeh, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
pp. 262
Author Index
Usage of this product signifies your acceptance of the Terms of Use.