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Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Defect-Oriented Analysis of Memory BIST Tests
Isle of Bendor, France
July 08-July 10
ISBN: 0-7695-1641-6
| ASCII Text | x | ||
| Alvin Jee, "Defect-Oriented Analysis of Memory BIST Tests," On-Line Testing Workshop, IEEE International, pp. 201, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002. | |||
| BibTex | x | ||
| @article{ 10.1109/OLT.2002.1030219, author = {Alvin Jee}, title = {Defect-Oriented Analysis of Memory BIST Tests}, journal ={On-Line Testing Workshop, IEEE International}, volume = {0}, year = {2002}, isbn = {0-7695-1641-6}, pages = {201}, doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2002.1030219}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - On-Line Testing Workshop, IEEE International TI - Defect-Oriented Analysis of Memory BIST Tests SN - 0-7695-1641-6 SP EP A1 - Alvin Jee, PY - 2002 KW - null VL - 0 JA - On-Line Testing Workshop, IEEE International ER - | |||
This paper describes defect-oriented analysis of 4 BIST tests that are used to test a commercial 6-port embedded SRAM. We will examine the realistic fault and defect coverages of these memory BIST tests. We also uncover the subtle effect that addressing order has on the coverage that a test can provide. In addition, we will show that the coverage that a test provides can vary from row to row depending on the addressing scheme.
Citation:
Alvin Jee, "Defect-Oriented Analysis of Memory BIST Tests," ioltw, pp.201, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002
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