The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay, testing using external testers requires expensive ATE; built-in self-test (BIST) is an alternative technique that can significantly reduce the test cost. The generation of test patterns in this case is usually pseudo-random (produced from an LFSR), and it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when high robust delay fault coverage is targeted. In this paper, we first question the use of a pseudo-random generation to produce effective delay test pairs. We demonstrate that using truly random test pairs (produced from a software generation) to test path delay faults in a given circuit produces higher delay fault coverage than that obtained with pseudo-random test pairs obtained from a classical primitive LFSR. Next, we show that the same conclusion can be drawn when stuck-at or bridging fault coverage is targeted rather delay fault coverage. A modified hardware TPG structure allowing the generation of truly random test patterns is introduced at the end of the paper.