With the ever increasing data throughputs required by communication application, there is an actual need for new effective architectures (small area and high speed) for circuit parts dedicated to error detecting/correcting coding (EDC/ECC). In this paper, we propose a new parallel-pipeline design scheme for convolution encoders that meets these requisites. This approach apply both to the OTM (One To Many) and the MTO (Many To One) encoder variants. Here, we will focus only on the OTM case to prove the effectiveness of this new architecture. In order to evaluate the complexity/performance tradeoff and validate the architecture, several encoders have been implemented on FPGA devices of the Altera Stratix II family corresponding to different convolutional codes and parallelization levels. It is obvious from the experimental results the new architecture outperforms the former ones, including those proposed by us in [1] for OTM and MTO. Indeed, similar bit rates have been achieved with noticeable area consumption reduction (up to 8.10 Gbits/s achieved with a 58% smaller circuit in the case of 32-bit parallel implementations).