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Sesimbra-Lisbon, Portugal
June 24, 2009 to June 26, 2009
ISBN: 978-1-4244-4596-7
pp: 237-242
Amit Dutta , Texas Instruments, Bangalore, India
Malav Shah , Texas Instruments, Bangalore, India
G. Swathi , Texas Instruments, Bangalore, India
Rubin A. Parekhji , Texas Instruments, Bangalore, India
Periodic testing of electronic devices on the field during application execution is becoming increasingly important. In addition, some of these applications are embedded and real-time, requiring the system to be operational for extended periods. In such applications, field test must be cleverly interleaved with normal operation, such that the latter is not impacted, while at the same time guaranteeing the correct operation of the device, and identification of any malfunction or defects within a reasonable time. This paper discusses the design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test. Three specific designs aspects are discussed, namely (i) choice of logic BIST self-test architecture, (ii) optimizations in test time and additional memory requirements for attaining a given coverage, and (iii) DUT interface to self-test DFT logic to enable such form of test and application interleaving. Data is presented for an IP core, which is presently being designed in Texas Instruments (India), wherein such tests are being supported for use in automotive applications.
Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji, "Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test", IOLTS, 2009, 11th IEEE International On-Line Testing Symposium, 11th IEEE International On-Line Testing Symposium 2009, pp. 237-242, doi:10.1109/IOLTS.2009.5196022
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