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Sesimbra-Lisbon, Portugal
June 24, 2009 to June 26, 2009
ISBN: 978-1-4244-4596-7
pp: 212-214
ABSTRACT
This paper evaluates fault-tolerant behavior of an NoC router through simulation-based method. A structural-level VHDL environment has been employed to estimate fault injector signal's (FIS) effects. Different fault models such as dead clause, stuck-then, micro-operation, crosstalk, and SEU have been injected to evaluate the transient faults' effects. According to the results, up to 48% of the injected faults cause system failure and also about 51% are overwritten before turning into errors. Less than 1% of injected faults treat as latent errors. The average of fault latency has been investigated as 194ns. Almost 70%, 31%, and 35% of injected faults are overwritten in buffer, routing unit, and switch components, respectively. Routing unit is also recognized as the most tenuous component.
INDEX TERMS
Network-on-a-chip, Circuit faults, Routing, Fault tolerance, Switches, Clocks, Single event upset, Crosstalk, Topology, Electromagnetic radiation
CITATION
"Fault injection-based evaluation of a synchronous NoC router", IOLTS, 2009, 11th IEEE International On-Line Testing Symposium, 11th IEEE International On-Line Testing Symposium 2009, pp. 212-214, doi:10.1109/IOLTS.2009.5196018
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