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2009 15th IEEE International On-Line Testing Symposium
Analysis of the extra delay on interconnects caused by resistive opens and shorts
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
Pablo Maqueda, Dept. Enginyeria Electrònica, Universitat Politècnica de Catalunya, Diagonal 647, 9th floor, 08028 Barcelona, Spain
Josep Rius, Dept. Enginyeria Electrònica, Universitat Politècnica de Catalunya, Diagonal 647, 9th floor, 08028 Barcelona, Spain
The paper presents an analytical solution for the delay introduced by opens and shorts on RC interconnects. Starting from the set of PDEs that defines the dynamics of such lines, complete solutions are found. Compact expressions for the delay, derived from the complete solutions, show an excellent agreement when compared with simulations, for realistic values of interconnect parameters, driver resistance and an arbitrary values and place of the defect. This information is useful for testing of such interconnects.
Citation:
Pablo Maqueda, Josep Rius, "Analysis of the extra delay on interconnects caused by resistive opens and shorts," iolts, pp.208-209, 2009 15th IEEE International On-Line Testing Symposium, 2009
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