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2009 15th IEEE International On-Line Testing Symposium
An Input Vector Monitoring Concurrent BIST scheme exploiting
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
I. Voyiatzis, Deparetment of Informatics, Technological Educational Institute of Athens, Aigaleo, Greece
D. Gizopoulos, Department of Informatics, University of Pireaus, Greece
A. Paschalis, Department of Informatics&Telecommunications, University of Athens, Greece
Input Vector Monitoring Concurrent Built-In Self Test schemes provide the capability to perform testing while the Circuit Under Test operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. The Concurrent Test Latency of an input vector monitoring scheme is the time required for the concurrent test to complete. Input Vector Monitoring Concurrent BIST schemes that have been proposed to date, are based mainly on test sets containing binary (1 or 0) values. Test sets extracted by modern CAD tools, largely contain don't care (‘X’) values. In this work a novel input vector monitoring concurrent BIST scheme is presented, based on a test set containing ‘X’ values. The proposed scheme compares favourably with respect to the hardware overhead - concurrent test latency trade off with previously proposed techniques.
Citation:
I. Voyiatzis, D. Gizopoulos, A. Paschalis, "An Input Vector Monitoring Concurrent BIST scheme exploiting ," iolts, pp.206-207, 2009 15th IEEE International On-Line Testing Symposium, 2009
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