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2009 15th IEEE International On-Line Testing Symposium
A fault tolerant journalized stack processor architecture
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
Abbas Ramazani, LICM Laboratory, University Paul Verlaine - Metz, 7 rue Marconi, 57070, France
Mohsin Amin, LICM Laboratory, University Paul Verlaine - Metz, 7 rue Marconi, 57070, France
Fabrice Monteiro, LICM Laboratory, University Paul Verlaine - Metz, 7 rue Marconi, 57070, France
Camille Diou, LICM Laboratory, University Paul Verlaine - Metz, 7 rue Marconi, 57070, France
Abbas Dandache, LICM Laboratory, University Paul Verlaine - Metz, 7 rue Marconi, 57070, France
Dependable architectures play an important role in many areas that impact our lives. Dependability is achieved by using a set of analysis and design techniques that increases the complexity and consequently the cost of systems. In this paper, to meet low cost requirement of IP cores, we propose a simple dependable stack processor architecture using a re-execution model of instructions in the case of error detection in consecutive sequences of instructions execution. The architecture is based on applying two memory journals as intermediate stages between processor and main memory in write operations. Then, we present the results obtained by using the developed emulation tools.
Citation:
Abbas Ramazani, Mohsin Amin, Fabrice Monteiro, Camille Diou, Abbas Dandache, "A fault tolerant journalized stack processor architecture," iolts, pp.201-202, 2009 15th IEEE International On-Line Testing Symposium, 2009
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