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2009 15th IEEE International On-Line Testing Symposium
FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
Junfeng Fan, Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Miroslav Knezevic, Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Dusko Karaklajic, Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Roel Maes, Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Vladimir Rozic, Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Lejla Batina, Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Ingrid Verbauwhede, Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Testing of cryptographic chips or components has one extra dimension: physical security. The chip designers should improve the design if it leaks too much information through side-channels, such as timing, power consumption, electric-magnetic radiation, and so on. This requires an evaluation of the security level of the chip under different side-channel attacks before it is manufactured. This paper presents an FPGA-based testing strategy for cryptographic chips. Using a block-based architecture, a testing bus and a shadow FPGA, we are able to check information leakage of each block. We describe this strategy with an Elliptic Curve Cryptosystem (ECC) for RFID tags.
Citation:
Junfeng Fan, Miroslav Knezevic, Dusko Karaklajic, Roel Maes, Vladimir Rozic, Lejla Batina, Ingrid Verbauwhede, "FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags," iolts, pp.189-191, 2009 15th IEEE International On-Line Testing Symposium, 2009
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