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2009 15th IEEE International On-Line Testing Symposium
Briefing power/reliability optimization in embedded software design
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
Fabian Vargas, Electrical Engineering Dept., Catholic University - PUCRS, Av. Ipiranga, 6681., 90619-900 Porto Alegre - Brazil
Claudia A. Rocha, Electrical Engineering Dept., Catholic University - PUCRS, Av. Ipiranga, 6681., 90619-900 Porto Alegre - Brazil
Bernardo Pianta, Electrical Engineering Dept., Catholic University - PUCRS, Av. Ipiranga, 6681., 90619-900 Porto Alegre - Brazil
Marta Portela Garcia, Microelectronic Design and Applications, University Carlos III of Madrid, Av. Universidad, 30., 28911, Leganés, Spain
Celia Lopez Ongil, Microelectronic Design and Applications, University Carlos III of Madrid, Av. Universidad, 30., 28911, Leganés, Spain
Mario Garcia Valderas, Microelectronic Design and Applications, University Carlos III of Madrid, Av. Universidad, 30., 28911, Leganés, Spain
Luis Entrena, Microelectronic Design and Applications, University Carlos III of Madrid, Av. Universidad, 30., 28911, Leganés, Spain
We propose an approach1 to optimize the number of checkpoints to be inserted along with an application code. The approach is based on a profiling process that analyzes the application code control-flow graph to find the best trade-off between the minimum number of checkpoints to be inserted in the code for a given fault detection coverage, with minimum impact in terms of power increase. The checkpoints are verified at runtime by the processor against compilation-time pre-computed values every time the processor reaches these points. Experiments with a PIC18 microcontroller have been carried out to demonstrate the benefits from using the proposed approach.
Citation:
Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela Garcia, Celia Lopez Ongil, Mario Garcia Valderas, Luis Entrena, "Briefing power/reliability optimization in embedded software design," iolts, pp.185-186, 2009 15th IEEE International On-Line Testing Symposium, 2009
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