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2009 15th IEEE International On-Line Testing Symposium
Designing dependable multicore system with unreliable components
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
Vikas Chandra, ARM R&D, USA
Single core chip architecture do not scale well due to various design and reliability challenges. Multicore system with large numbers of cores are becoming common to take advantage of Moore's law. However, there exist various reliability concerns in nanoscale era due to spatial, temporal and dynamic variations. The only way to enable sustained scaling of multicore systems is to make the architecture robust by using adaptive design techniques and having redundant cores which can replace faulty ones.
Citation:
Vikas Chandra, "Designing dependable multicore system with unreliable components," iolts, pp.154, 2009 15th IEEE International On-Line Testing Symposium, 2009
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