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2009 15th IEEE International On-Line Testing Symposium
In-depth analysis of digital circuits against soft errors for selective hardening
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
Mario Garcia-Valderas, Microelectronic Design and Applications Group, Electronic Technology Dept., Carlos III University of Madrid, Spain
Marta Portela-Garcia, Microelectronic Design and Applications Group, Electronic Technology Dept., Carlos III University of Madrid, Spain
Celia Lopez-Ongil, Microelectronic Design and Applications Group, Electronic Technology Dept., Carlos III University of Madrid, Spain
Luis Entrena, Microelectronic Design and Applications Group, Electronic Technology Dept., Carlos III University of Madrid, Spain
SEU effects are a main concern in an increasing number of applications. Selective hardening in early design stages is intended to design a robust circuit in a fast and cost-efficient way. In this paper, a method to performing selective hardening in digital circuits against SEUs is described. This method is based on the Autonomous Emulation fault injection technique. It allows the designer to identify the critical parts of the circuit and use different hardening techniques to reach a trade-off between the obtained robustness and area and performance penalties. A PIC microcontroller has been analysed in detailed against SEU effects as case study, injecting millions of faults. Results points out that hardening just 17% of the circuit flip-flops reduces the failure rate induced by SEUs in 99%.
Citation:
Mario Garcia-Valderas, Marta Portela-Garcia, Celia Lopez-Ongil, Luis Entrena, "In-depth analysis of digital circuits against soft errors for selective hardening," iolts, pp.144-149, 2009 15th IEEE International On-Line Testing Symposium, 2009
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