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2009 15th IEEE International On-Line Testing Symposium
Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
Jose Rodrigo Azambuja, Universidade Federal do Rio Grande do Sul (UFRGS), Instituto de Informática, Av. Bento Gonçalves 9500, Porto Alegre - RS - Brazil
Fernando Sousa, Universidade Federal do Rio Grande do Sul (UFRGS), Instituto de Informática, Av. Bento Gonçalves 9500, Porto Alegre - RS - Brazil
Lucas Rosa, Universidade Federal do Rio Grande do Sul (UFRGS), Instituto de Informática, Av. Bento Gonçalves 9500, Porto Alegre - RS - Brazil
Fernanda Lima Kastensmidt, Universidade Federal do Rio Grande do Sul (UFRGS), Instituto de Informática, Av. Bento Gonçalves 9500, Porto Alegre - RS - Brazil
This paper presents an innovative method that allows the use of dynamic partial reconfiguration combined with triple modular redundancy (TMR) in SRAM-based FPGAs fault-tolerant designs. The method combines large grain TMR with special voters capable of signalizing the faulty module and check point states that allow the sequential synchronization of the recovered module with the Xilinx TMR (XTMR) approach. As a result, only the faulty domain is reconfigured, minimizing time and energy spent in the process. In addition, the use of checkpoint states avoids system downtime, since the synchronization of the recovered module is performed while the others are kept running. Experimental results show that the method has a reduced fault recovery time compared to the standard TMR implementation, maintaining the compatible area overhead and performance.
Citation:
Jose Rodrigo Azambuja, Fernando Sousa, Lucas Rosa, Fernanda Lima Kastensmidt, "Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs," iolts, pp.101-106, 2009 15th IEEE International On-Line Testing Symposium, 2009
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