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2009 15th IEEE International On-Line Testing Symposium
Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
| ASCII Text | x | ||
| Jose Rodrigo Azambuja, Fernando Sousa, Lucas Rosa, Fernanda Lima Kastensmidt, "Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs," 11th IEEE International On-Line Testing Symposium, pp. 101-106, 2009 15th IEEE International On-Line Testing Symposium, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/IOLTS.2009.5195990, author = {Jose Rodrigo Azambuja and Fernando Sousa and Lucas Rosa and Fernanda Lima Kastensmidt}, title = {Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs}, journal ={11th IEEE International On-Line Testing Symposium}, volume = {0}, year = {2009}, isbn = {978-1-4244-4596-7}, pages = {101-106}, doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2009.5195990}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 11th IEEE International On-Line Testing Symposium TI - Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs SN - 978-1-4244-4596-7 SP101 EP106 A1 - Jose Rodrigo Azambuja, A1 - Fernando Sousa, A1 - Lucas Rosa, A1 - Fernanda Lima Kastensmidt, PY - 2009 VL - 0 JA - 11th IEEE International On-Line Testing Symposium ER - | |||
This paper presents an innovative method that allows the use of dynamic partial reconfiguration combined with triple modular redundancy (TMR) in SRAM-based FPGAs fault-tolerant designs. The method combines large grain TMR with special voters capable of signalizing the faulty module and check point states that allow the sequential synchronization of the recovered module with the Xilinx TMR (XTMR) approach. As a result, only the faulty domain is reconfigured, minimizing time and energy spent in the process. In addition, the use of checkpoint states avoids system downtime, since the synchronization of the recovered module is performed while the others are kept running. Experimental results show that the method has a reduced fault recovery time compared to the standard TMR implementation, maintaining the compatible area overhead and performance.
Citation:
Jose Rodrigo Azambuja, Fernando Sousa, Lucas Rosa, Fernanda Lima Kastensmidt, "Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs," iolts, pp.101-106, 2009 15th IEEE International On-Line Testing Symposium, 2009
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