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Sesimbra-Lisbon, Portugal
June 24, 2009 to June 26, 2009
ISBN: 978-1-4244-4596-7
pp: 81-86
X. Vera , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya, Barcelona, Spain
J. Abella , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya, Barcelona, Spain
J. Carretero , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya, Barcelona, Spain
P. Chaparro , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya, Barcelona, Spain
A. Gonzalez , Intel Barcelona Research Center, Intel Labs - Universitat Politècnica de Catalunya, Barcelona, Spain
ABSTRACT
Aggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAM cell. Gate oxide scaling can cause large transient gate leakage (a trap in the gate oxide), which is known as the erratic bits phenomena. Register file protection is necessary to prevent errors from quickly spreading to different parts of the system, which may cause applications to crash or silent data corruption. This paper proposes a simple and cost-effective mechanism that increases the resiliency of the register files to erratic bits. Our mechanism detects those registers that have erratic bits, recovers from the error and quarantines the faulty register. After the quarantine period, it is able to detect whether they are fully operational with low overhead.
CITATION
X. Vera, J. Abella, J. Carretero, P. Chaparro, A. Gonzalez, "Online error detection and correction of erratic bits in register files", IOLTS, 2009, 11th IEEE International On-Line Testing Symposium, 11th IEEE International On-Line Testing Symposium 2009, pp. 81-86, doi:10.1109/IOLTS.2009.5195987
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