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2009 15th IEEE International On-Line Testing Symposium
Comparing transient-fault effects on synchronous and on asynchronous circuits
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
R. Possamai Bastos, TIMA Laboratory, INPG, Grenoble, France
Y. Monnet, TIEMPO, Montbonnot St Martin, France
G. Sicard, TIMA Laboratory, INPG, Grenoble, France
F. Kastensmidt, UFRGS, Instituto de Informática, PGMicro, Porto Alegre, Brazil
M. Renaudin, TIEMPO, Montbonnot St Martin, France
R. Reis, UFRGS, Instituto de Informática, PGMicro, Porto Alegre, Brazil
A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the particularities of asynchronous circuits. Unlike previous works, it permits to compare the sensitivity of circuits designed by synchronous and asynchronous logics. The resultant metrics allow identifying at high-level abstraction what is the logic that makes the circuit more transient-fault sensitive. As a case study, a crypto-processor in versions synchronous and asynchronous was evaluated.
Citation:
R. Possamai Bastos, Y. Monnet, G. Sicard, F. Kastensmidt, M. Renaudin, R. Reis, "Comparing transient-fault effects on synchronous and on asynchronous circuits," iolts, pp.29-34, 2009 15th IEEE International On-Line Testing Symposium, 2009
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