June 24, 2009 to June 26, 2009
Y. Monnet , TIEMPO, Montbonnot St Martin, France
G. Sicard , TIMA Laboratory, INPG, Grenoble, France
F. Kastensmidt , UFRGS, Instituto de Informática, PGMicro, Porto Alegre, Brazil
R. Possamai Bastos , TIMA Laboratory, INPG, Grenoble, France
R. Reis , UFRGS, Instituto de Informática, PGMicro, Porto Alegre, Brazil
A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the particularities of asynchronous circuits. Unlike previous works, it permits to compare the sensitivity of circuits designed by synchronous and asynchronous logics. The resultant metrics allow identifying at high-level abstraction what is the logic that makes the circuit more transient-fault sensitive. As a case study, a crypto-processor in versions synchronous and asynchronous was evaluated.
Y. Monnet, G. Sicard, F. Kastensmidt, R. Possamai Bastos, R. Reis, "Comparing transient-fault effects on synchronous and on asynchronous circuits", IOLTS, 2009, 11th IEEE International On-Line Testing Symposium, 11th IEEE International On-Line Testing Symposium 2009, pp. 29-34, doi:10.1109/IOLTS.2009.5195979