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2009 15th IEEE International On-Line Testing Symposium
A methodology for measuring transistor ageing effects towards accurate reliability simulation
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
Elie Maricau, ESAT-MICAS KULeuven, Heverlee, Belgium 3001
Georges Gielen, ESAT-MICAS KULeuven, Heverlee, Belgium 3001
Emerging die-level stress effects (i.e. NBTI, HCI, TDDB, etc.) in nanometer CMOS technologies cause both analog and digital circuit parameters to degrade over time. To efficiently evaluate these degradation effects in modern ICs, a reliability simulator, using accurate first order degradation models, is needed. In this work, we propose a new measurement workflow addressing several modelling and measurement issues involved with developing these new degradation models. A new on-the-fly measurement technique, avoiding complicated NBTI relaxation problems, is introduced. This technique provides a complete set of easy-to-use modelling parameters and allows the modelling of both DC and AC stress effects in all transistor operating regions. To eliminate large extrapolation errors, we also propose a simple measurement circuit suited for fast and accurate degradation modelling at nominal voltages and temperatures. Avoiding the use of complicated and technology restricted transistor models, this new methodology is very flexible and can be used over a broad range of nanometer CMOS processes.
Citation:
Elie Maricau, Georges Gielen, "A methodology for measuring transistor ageing effects towards accurate reliability simulation," iolts, pp.21-26, 2009 15th IEEE International On-Line Testing Symposium, 2009
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