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2009 15th IEEE International On-Line Testing Symposium
An I-IP based approach for the monitoring of NBTI effects in SoCs
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
C. Guardiani, Elite-DC S.r.l., Italy
A. Shibkov, Elite-DC S.r.l., Italy
A. Brambilla, Politecnico di Milano, Italy
G. Storti Gajani, Politecnico di Milano, Italy
D. Appello, ST Microelectronics S.r.l., Italy
F. Piazza, ST Microelectronics S.r.l., Italy
P. Bernardi, Politecnico di Torino, Italy
In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor VTH degradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensation scheme that automatically detects transistor aging effects and illustrates the design for test infrastructure used to make the SoC/System aware of the NBTI effects. This scheme is conceptually validated by using multi-level simulation and models. The discussion of possible exploitation models completes the paper.
Citation:
C. Guardiani, A. Shibkov, A. Brambilla, G. Storti Gajani, D. Appello, F. Piazza, P. Bernardi, "An I-IP based approach for the monitoring of NBTI effects in SoCs," iolts, pp.15-20, 2009 15th IEEE International On-Line Testing Symposium, 2009
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