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2009 15th IEEE International On-Line Testing Symposium
Aging analysis of circuit timing considering NBTI and HCI
Sesimbra-Lisbon, Portugal
June 24-June 26
ISBN: 978-1-4244-4596-7
Dominik Lorenz, Institute for Electronic Design Automation, Technische Universität München, Munich, Germany
Georg Georgakos, Infineon Technologies AG, Neubiberg, Germany
Ulf Schlichtmann, Institute for Electronic Design Automation, Technische Universität München, Munich, Germany
We present an aging analysis flow able to calculate the degraded circuit timing. To the best of our knowledge it is the first approach on gate level so far capable of analyzing the impact of the two dominant drift-related aging effects - NBTI and HCI - on complex digital circuits. The aging-aware gate model used to compute the aged circuit timing provides not just the cell delay degradation, but also the degradation of the output slope. To get more accurate results, the individual workload of a gate can be considered.
Citation:
Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann, "Aging analysis of circuit timing considering NBTI and HCI," iolts, pp.3-8, 2009 15th IEEE International On-Line Testing Symposium, 2009
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