CSDL - Proceedings I

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-ix

Message from General Chair(s) (PDF)

pp. x

IOLTS 2008 Committees (PDF)

pp. xi

Program Committee (PDF)

pp. xii

Test Technology Technical Council (PDF)

pp. xiii-xv

Test Technology Educational Program (TTEP) 2008 Full-Day Tutorial (PDF)

pp. xvi-xvii

On-Line Failure Detection and Confinement in Caches (Abstract)

pp. 3-9

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An Enhanced Logic BIST Architecture for Online Testing (Abstract)

Fan Yang

Sreejit Chakravarty

Narendra Devta-Prasanna

Sudhakar M. Reddy

Irith Pomeranz

pp. 10-15

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Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection (Abstract)

pp. 16-21

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Verification and Analysis of Self-Checking Properties through ATPG (Abstract)

Marc Hunger

Sybille Hellebrand

pp. 25-30

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Physical Demonstration of Polymorphic Self-Checking Circuits (Abstract)

pp. 31-36

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New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability (Abstract)

pp. 37-42

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Special Session 1: Radiation Hardening Techniques (Abstract)

Norbert Seifert

pp. 43-44

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Soft Error Protection Techniques (Abstract)

Subhasish Mitra

pp. 45

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Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS (Abstract)

pp. 46-48

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Soft Error Rates of Hardened Sequentials utilizing Local Redundancy (Abstract)

Norbert Seifert

pp. 49-50

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False Error Study of On-line Soft Error Detection Mechanisms (Abstract)

pp. 53-58

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Integrating Scan Design and Soft Error Correction in Low-Power Applications (Abstract)

Michael E. Imhof

Hans-Joachim Wunderlich

Christian G. Zoellin

pp. 59-64

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A Built-In Self-Test Scheme for Soft Error Rate Characterization (Abstract)

pp. 65-70

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Budget-Dependent Control-Flow Error Detection (Abstract)

Ramtilak Vemu

Jacob A. Abraham

pp. 73-78

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Software Self-Testing of a Symmetric Cipher with Error Detection Capability (Abstract)

pp. 79-84

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A Fault-Tolerant Attitude Determination System Based on COTS Devices (Abstract)

Ricardo O. Duarte

Luiz S. Martins-Filho

Guilherme F.T. Knop

Ricardo S. Prado

pp. 85-90

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A New Approach for Transient Fault Injection Using Symbolic Simulation (Abstract)

pp. 93-98

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SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation (Abstract)

pp. 99-104

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Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force? (Abstract)

Michael Nicolaidis

pp. 105-106

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A Systematical Method of Quantifying SEU FIT (Abstract)

pp. 109-114

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Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs (Abstract)

pp. 117-122

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On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD (Abstract)

pp. 123-128

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Propagation of Transients Along Sensitizable Paths (Abstract)

pp. 129-134

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On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs (Abstract)

Niccol? Battezzati

Simone Gerardin

Andrea Manuzzato

Alessandro Paccagnella

pp. 135-140

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A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs (Abstract)

pp. 143-148

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A BISR Architecture for Embedded Memories (Abstract)

pp. 149-154

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Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement (Abstract)

pp. 155-160

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Special Session 3 ? Panel: SER in Automotive: what is the impact of the AEC Q100-G spec? (Abstract)

Tino Heijmen

pp. 161-162

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Yield Improvement, Fault-Tolerance to the Rescue? (Abstract)

J. Vial

pp. 165-166

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Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard (Abstract)

Celia L?pez-Ongil

Alejandro Jim?nez-Horas

Marta Portela-Garc?

Mario Garc?a-Valderas

Enrique San Mill?

Luis Entrena

pp. 167-168

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SRAM Cell Design Protected from SEU Upsets (Abstract)

pp. 169-170

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A Modular Memory BIST for Optimized Memory Repair (Abstract)

pp. 171-172

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A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing (Abstract)

pp. 173-174

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A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies (Abstract)

Zhengfeng Huang

Huaguo Liang

pp. 175-176

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Basic Architecture for Logic Self Repair (Abstract)

Tobias Koal

Heinrich T. Vierhaus

pp. 177-178

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Developing Fault Injection Environment for Complex Experiments (Abstract)

P. Gawkowski

J. Sosnowski

pp. 179-181

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Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448 (Abstract)

pp. 182-184

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Dynamic Scheduling of Test Routines for Efficient Online Self-Testing of Embedded Microprocessors (Abstract)

pp. 185-187

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Fault Tolerant Reversible Finite Field Arithmetic Circuits (Abstract)

pp. 188-189

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On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous Element (Abstract)

pp. 190-191

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Totally Fault Tolerant RNS Based FIR Filters (Abstract)

M. Re

pp. 192-194

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Special Session 4: Reliability and Circuit Simulation (Abstract)

Rob Aitken

pp. 195-196

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Modeling and Simulation of Circuit Aging in Scaled CMOS Design (Abstract)

Yu (Kevin) Kao

pp. 197

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Communication Aware Recovery Configurations for Networks-on-Chip (Abstract)

pp. 201-206

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Reliability in Application Specific Mesh-Based NoC Architectures (Abstract)

pp. 207-212

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On-Line Testing of Lab-on-Chip Using Digital Microfluidic Compactors (Abstract)

Yang Zhao

Krishnendu Chakrabarty

pp. 213-218

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Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips (Abstract)

pp. 219-224

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Juan Jose Rodr?guez-Andina

Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits (Abstract)

Jorge Semi?

Judit Freijedo

pp. 227-232

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On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring (Abstract)

pp. 233-238

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Guided Probabilistic Checksums for Error Control in Low Power Digital-Filters (Abstract)

Muhammad Mudassar Nisar

Abhijit Chatterjee

pp. 239-244

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Soft-Error Vulnerability of Sub-100-nm Flip-Flops (Abstract)

Tino Heijmen

pp. 247-252

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Variation of SRAM Alpha-Induced Soft Error Rate with Technology Node (Abstract)

pp. 253-257

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Deterministic Built-in TPG with Segmented FSMs (Abstract)

pp. 261-266

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A Low-Cost Accumulator-Based Test Pattern Generation Architecture (Abstract)

pp. 267-272

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Directed Random SBST Generation for On-Line Testing of Pipelined Processors (Abstract)

pp. 273-279

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SDRAM Architecture & Single Event Effects Revealed with Laser (Abstract)

pp. 283-288

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Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA (Abstract)

pp. 289-294

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Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault Injection (Abstract)

pp. 295-301

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Author Index (PDF)

pp. 303-305

Roster Page (PDF)

pp. 306