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13th IEEE International On-Line Testing Symposium (IOLTS 2007)
Heraklion, Crete, Greece
July 08-July 11
ISBN: 0-7695-2918-6
ASCII Text
x 
 
R. Mariani, G. Boschi, "A systematic approach for Failure Modes and Effects Analysis of System-On-Chips," 11th IEEE International On-Line Testing Symposium, pp. 187-188, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007.
 
 
BibTex
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@article{ 10.1109/IOLTS.2007.10,
author = {R. Mariani and G. Boschi},
title = {A systematic approach for Failure Modes and Effects Analysis of System-On-Chips},
journal ={11th IEEE International On-Line Testing Symposium},
volume = {0},
year = {2007},
isbn = {0-7695-2918-6},
pages = {187-188},
doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.10},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - 11th IEEE International On-Line Testing Symposium
TI - A systematic approach for Failure Modes and Effects Analysis of System-On-Chips
SN - 0-7695-2918-6
SP187
EP188
A1 - R. Mariani,
A1 - G. Boschi,
PY - 2007
KW - null
VL - 0
JA - 11th IEEE International On-Line Testing Symposium
ER -
 
R. Mariani, YOGITECH, Italy
G. Boschi, YOGITECH, Italy
This paper proposes a method to perform Failure Mode and Effects Analysis (FMEA) on System-On- Chips (SoC). An automatic tool extracts information from the SoC description and uses them to estimate the intrinsic criticality of invariant and elementary "sensitive zones" and to compute metrics such failure rates, safe failures fraction and diagnostic coverage. A validation flow based on fault injection and fault simulation is included to cross check the FMEA.
Citation:
R. Mariani, G. Boschi, "A systematic approach for Failure Modes and Effects Analysis of System-On-Chips," iolts, pp.187-188, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
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