CSDL - Proceedings I

Organizing Committee (PDF)

pp. x

Program Committee (PDF)

pp. xi

TTTC: Test Technology Technical Council (PDF)

pp. xii-xiv

Keynote Talk

The Challenge of Reliability in Future Complex Systems (PDF)

Andrea Cuomo, STMicroelectronics

pp. 3

Invited Talk

Extending Moore's Law into the next Decade - the SER Challenge (PDF)

Norbert Seifert, Intel Corporation

pp. 7

Session 1: Fault Effects and Self-Checking Techniques

Characterizing Laser-Induced Pulses in ICs: Methodology and Results (Abstract)

D. Leroy, iRoC Technologies SA

S. J. Piestrak, University of Metz, France

F. Monteiro, University of Metz, France

A. Dandache, University of Metz, France

S. Rossignol, iRoC Technologies SA

P. Moitrel, Gemplus

pp. 11-16

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Path (Min) Delay Faults and Their Impact on Self-Checking Circuits? Operation (Abstract)

C. Metra, University of Bologna, Italy

M. Oma?, University of Bologna, Italy

D. Rossi, University of Bologna, Italy

J. M. Cazeaux, University of Bologna, Italy

TM Mak, Intel Corporation, USA

pp. 17-22

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A New Self-Checking and Code-Disjoint Non-Restoring Array Divider (Abstract)

D. Marienfeld, University of Potsdam, Germany

E. S. Sogomonyan, University of Potsdam, Germany

V. Otcheretnij, University of Potsdam, Germany

M. G?ssel, University of Potsdam, Germany

pp. 23-30

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Session 2: BIST Techniques

Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor (Abstract)

Swaroop Ghosh, Purdue University, USA

Swarup Bhunia, Purdue University, USA

Arijit Raychowdhury, Purdue University, USA

Kaushik Roy, Purdue University, USA

pp. 31-36

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A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST (Abstract)

Chaowen Yu, University of Iowa, USA

Sudhakar M. Reddy, University of Iowa, USA

Irith Pomeranz, Purdue University, USA

pp. 37-42

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Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding (Abstract)

Stelios Neophytou, University of Cyprus, Cyprus

Maria K. Michael, University of Cyprus, Cyprus

Spyros Tragoudas, Southern Illinois University, USA

pp. 43-50

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Session 3: Technology Robustness

Erratic Effects of Irradiation in Floating Gate Memory Cells (Abstract)

G. Cellere, Padova University, Italy

A. Paccagnella, Padova University, Italy

A. Visconti, STMicroelectronics, Italy

M. Bonanomi, STMicroelectronics, Italy

pp. 51-56

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Factors That Impact the Critical Charge of Memory Elements (Abstract)

Tino Heijmen, Philips Research Laboratories (WAY41), The Netherlands

Damien Giot, ST Microelectronics, France

Philippe Roche, ST Microelectronics, France

pp. 57-62

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Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells (Abstract)

G. Hubert, EADS, Corporate Research Center

A. Bougerol, EADS, Corporate Research Center

F. Miller, EADS, Corporate Research Center

N. Buard, EADS, Corporate Research Center

L. Anghel, TIMA Laboratory

T. Carriere, EADS, Space Transportation

F. Wrobel, University of Nice-Sophia Antipolis

R. Gaillard, INFODUC

pp. 63-74

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Special Session 1: Memory Reliability Challenges

Embedded Memory Reliability Trends and Solutions

Reliability Issues for Embedded SRAM at 90nm and Below (PDF)

Rob Aitken, ARM, Inc., USA

pp. 75

Testing Strategies for Non Volatile Memory Reliability

Towards The Methodology of On-line Diagnosis (PDF)

Rochit Rajsuman, Advantest America Corporation, USA

pp. 76

Special Session 2: Test and Reliability Challenges for Innovative Systems

Test Challenges for 3D Circuits (PDF)

TM Mak, Intel Corporation

pp. 79

Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network (PDF)

Marcello Coppola, STMicroelectronics, France

pp. 80

Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs (PDF)

Magdy S. Abadir, Freescale Semiconductor Inc., USA

pp. 81

The Consequences of Variability in Software (PDF)

Isaac Levendel, Levendel & Associates

pp. 82

From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately? (PDF)

Panel 1

Lorena Anghel, TIMA

Michael Nicolaidis, TIMA

Nadine Buard, EADS-CCR

pp. 85

Fault Tolerance Implementation within SRAM Based FPGA Design Based upon the Increased Level of Single Event Upset Susceptibility (Abstract)

Embedded Tutorials: Innovative Design for Robustness

Melanie Berg, NASA Goddard Space Flight Center Radiation Effects and Analysis Group/MEI Technologies

pp. 89-91

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Asynchronous Design: Fault Robustness and Security Characteristics (Abstract)

Marc Renaudin, TIMA Laboratory, France

Yannick Monnet, TIMA Laboratory, France

pp. 92-95

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Session 4: Soft Errors and Latchup Mitigation

Combinational Logic Soft Error Analysis and Protection (Abstract)

Andre K. Nieuwland, Philips Research Eindhoven, Netherlands

Samir Jasarevic, Philips Semiconductors, UK

Goran Jerin, Lund University, Sweden

pp. 99-104

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An Improved Technique for Reducing False Alarms Due to Soft Errors (Abstract)

Sandip Kundu, University of Massachusets, USA

Ilia Polian, Albert-Ludwigs-University of Freiburg, Germany

pp. 105-110

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A Low-Cost Single-Event Latchup Mitigation Sscheme (Abstract)

Michael Nicolaidis, TIMA Laboratory, France

pp. 111-118

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Session 5: Secure Circuits

Secure Scan Techniques: A Comparison (Abstract)

David H?ly, ST Microelectronics, France

Fr?d?ric Bancel, ST Microelectronics, France

Marie-Lise Flottes, Universit? Montpellier II, France

Bruno Rouzeyre, Universit? Montpellier II, France

pp. 119-124

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Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor (Abstract)

Y. Monnet, TIMA Laboratory, France

M. Renaudin, TIMA Laboratory, France

R. Leveugle, TIMA Laboratory, France

N. Feyt, Gemplus Card International, France

P. Moitrel, Gemplus Card International, France

F. M'Buwa Nzenguet, Gemplus Card International, France

pp. 125-130

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Power Attacks on Secure Hardware Based on Early Propagation of Data (Abstract)

Konrad J. Kulikowski, Boston University, USA

Mark G. Karpovsky, Boston University, USA

Alexander Taubin, Boston University, USA

pp. 131-138

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Session 6: Fault Detection Techniques

Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs (Abstract)

Maico Cassel, UFRGS, Brazil

Fernanda Lima Kastensmidt, UFRGS, Brazil

pp. 139-144

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On-line Fault Detection and Location for NoC Interconnects (Abstract)

Cristian Grecu, University of British Columbia, Canada

Andr? Ivanov, University of British Columbia, Canada

Res Saleh, University of British Columbia, Canada

Egor S. Sogomonyan, University of Potsdam, Germany

Partha Pratim Pande, Washington State University, USA

pp. 145-150

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CEDA: Control-flow Error Detection through Assertions (Abstract)

Ramtilak Vemu, University of Texas at Austin, USA

Jacob A. Abraham, University of Texas at Austin, USA

pp. 151-158

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Session 7: Analog Circuits Dependability

On-Line Error Detection in Wireless RF Transmitters Using Real-time Streaming Data (Abstract)

V. Natarajan, Georgia Institute of Technology

G. Srinivasan, Georgia Institute of Technology

A. Chatterjee, Georgia Institute of Technology

pp. 159-164

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Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study (Abstract)

Cristiano Lazzari, UFRGS, Brazil

Ricardo A. L. Reis, UFRGS, Brazil

Lorena Anghel, TIMA Laboratory, France

pp. 165-172

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Session 8: Posters

Embedded Borden 2-UED Code Checkers (Abstract)

Steffen Tarnick, 4TECH GmbH, Germany

pp. 173-175

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A Note on Error Detection in an RSA Architecture by Means of Residue Codes (PDF)

L. Breveglieri, Politecnico di Milano, Italy

P. Maistri, Politecnico di Milano, Italy

I. Koren, Univ. of Massachusetts, USA

pp. 176-177

Localization of Faults in Radix-n Signed Digit Adders (Abstract)

G.C. Cardarilli, University of Rome "Tor Vergata", Italy

M. Ottavi, University of Rome "Tor Vergata", Italy

S. Pontarelli,, University of Rome "Tor Vergata", Italy

M. Re, University of Rome "Tor Vergata", Italy

A. Salsano, University of Rome "Tor Vergata", Italy

pp. 178-180

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Embedded Scan Test with Diagnostic Features for Self-Testing SoCs (PDF)

C. Galke, Brandenburg University of Technology Cottbus

R. Kothe, Brandenburg University of Technology Cottbus

S. Schultke, Brandenburg University of Technology Cottbus

K. Winkler, Brandenburg University of Technology Cottbus

J. Honko, Brandenburg University of Technology Cottbus

H. T. Vierhaus, Brandenburg University of Technology Cottbus

pp. 181-182

Emulation-based Fault Injection in Circuits with Embedded Memories (PDF)

Mario Garc?a-Valderas, Carlos III University of Madrid. Spain

Marta Portela-Garc?, Carlos III University of Madrid. Spain

Celia L?pez-Ongil, Carlos III University of Madrid. Spain

Luis Entrena, Carlos III University of Madrid. Spain

pp. 183-184

Fault Tolerant System Design Method Based on Self-Checking Circuits (PDF)

Pavel Kubal?, Czech Technical University in Prague, Czech Republic

Petr Fiser, Czech Technical University in Prague, Czech Republic

Hana Kub?tov?, Czech Technical University in Prague, Czech Republic

pp. 185-186

Built-in Self Repair by Reconfiguration of FPGAs (PDF)

S. Habermann, Brandenburg University of Technology Cottbus, Germany

R. Kothe, Brandenburg University of Technology Cottbus, Germany

H. T. Vierhaus, Brandenburg University of Technology Cottbus, Germany

pp. 187-188

Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices (PDF)

L. Sterpone, Politecnico di Torino, Italy

M. Violante, Politecnico di Torino, Italy

pp. 189-190

Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers (PDF)

Arthur Pereira Frantz, UFRGS, Brazil

Luigi Carro, UFRGS, Brazil

?rika Cota, UFRGS, Brazil

Fernanda Lima Kastensmidt, UFRGS, Brazil

pp. 191-192

Diophantine-Equation Based Arithmetic Test Set Embedding (PDF)

D. Nikolos, University of Patras, Greece

D. Kagaris, Southern Illinois University, USA

S. Gidaros, University of Patras, Greece

pp. 193-194

Design of a Robust 8-Bit Microprocessor to Soft Errors (PDF)

Rodrigo Possamai Bastos, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil

Fernanda Lima Kastensmidt, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil

Ricardo Reis, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil

pp. 195-196

Panel 2

Should Logic SER be Solved at the Circuit Level? (PDF)

T. M. Mak, Intel Corporation

S. Mitra, Stanford University

pp. 199

Session 9: Reliable Systems

DMT and DT2: Two Fault-Tolerant Architectures developed by CNES for COTs-based Spacecraft Supercomputers (Abstract)

Michel Pignol Pignol, CNES, France

pp. 203-212

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Fault-Robust Microcontrollers for Automotive Applications (Abstract)

Riccardo Mariani, YOGITECH SpA

Peter Fuhrmann, Philips Research Laboratories

Boris Vittorelli, ARM Germany GmbH

pp. 213-218

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Contribution of Communications to Dependability in Massively-Defective General-Purpose Nanoarchitectures (Abstract)

Jacques Henri Collet, Universit? de Toulouse, France

Piotr Zajac, Technical University of Lodz, Poland

Yves Crouzet, Universit? de Toulouse, France

Andrzej Napieralski, Technical University of Lodz, Poland

pp. 219-228

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Session 10: Dependability Analysis

Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems (Abstract)

M. Sonza Reorda, Politecnico di Torino, Italy

M. Violante, Politecnico di Torino, Italy

pp. 229-234

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A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs (Abstract)

P. Kenterlis, University of Athens, Greece

N. Kranitis, University of Athens, Greece

A. Paschalis, University of Athens, Greece

D. Gizopoulos, University of Piraeus, Greece

M. Psarakis, University of Piraeus, Greece

pp. 235-241

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Real Time Fault Injection Using a Modified Debugging Infrastructure (Abstract)

Andr? V. Fidalgo, Instituto Superior de Engenharia do Porto, Portugal

Gustavo R. Alves, Instituto Superior de Engenharia do Porto, Portugal

Jos? M. Ferreira, Faculdade de Engenharia da Universidade do Porto, Portugal

pp. 242-250

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Session 11: New Topics in Fault Detection

The Problem of On-Line Testing Methods In Approximate Data Processing (Abstract)

A. Drozd, Odessa National Polytechnic University, Ukraine

M. Lobachev, Odessa National Polytechnic University, Ukraine

J. Drozd, Odessa National Polytechnic University, Ukraine

pp. 251-256

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Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes (Abstract)

M. Rodr?guez-Irago, IST/INESC-ID Lisboa, Portugal

J.J. Rodr?guez Andina, Univ. of Vigo, Spain

F. Vargas, PUCRS, Brazil

J. Semi?, INESC-ID / Univ. Algarve, Portugal

I.C. Teixeira, IST/INESC-ID Lisboa, Portugal

J.P. Teixeira, IST/INESC-ID Lisboa, Portugal

pp. 257-262

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Online Testing by Protocol Decomposition (Abstract)

Deepali Koppad, University of Newcastle upon Tyne, UK

Danil Sokolov, University of Newcastle upon Tyne, UK

Alex Bystrov, University of Newcastle upon Tyne, UK

Alex Yakovlev, University of Newcastle upon Tyne, UK

pp. 263-268

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Panel 3

Reliability in Automotive

Special Session 3: SER Trends: Vision and Developments from European IDMs

Soft Error Rates in Deep-Submicron CMOS Technologies (PDF)

Tino Heijmen, Philips Research Laboratories, The Netherlands

pp. 271

Trend in DRAM Soft Errors (PDF)

G?nter Schindlbeck, Infineon Technologies

pp. 272

Session 12: Checkers and Error Correction

Checker No-Harm Alarm Robustness (Abstract)

Daniele Rossi, D.E.I.S. University of Bologna, Italy

Martin x Martin Oma?, D.E.I.S. University of Bologna, Italy

Cecilia Metra, D.E.I.S. University of Bologna, Italy

Andrea Pagni, STMicroelectronics, Italy

pp. 275-280

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Designing Robust Checkers in the Presence of Massive Timing Errors (Abstract)

Frederic Worm, Ecole Polytechnique F?ed?erale de Lausanne

Patrick Thiran, Ecole Polytechnique F?ed?erale de Lausanne

Paolo Ienne, Ecole Polytechnique F?ed?erale de Lausanne

pp. 281-286

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Error Correction in Arithmetic Operations by I/O Inversion (Abstract)

Petros Oikonomakos, University of Cambridge, UK

Paul Fox, University of Cambridge, UK

pp. 287-292

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Author Index

Author Index (PDF)

pp. 293-294