Main stream scan test technology development has focused on a cost-efficient usage of external testers in conjunction with minimized on-chip pattern generators. Alternatively, an on-chip test processor that works with highly compacted test patterns from a ROM device allows a software-based self test procedure in the field of application, e.g. during startup tests. Furthermore, such an approach may facilitate self repair function, if the faulty logic block or gate can be identified. We present first investigations on an "embedded" scan-based fault diagnosis, efforts and limitations.