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11th IEEE International On-Line Testing Symposium
Saint Raphael, French Riviera, France
July 06-July 08
ISBN: 0-7695-2406-0
Table of Contents
Session 11: Timing, Yield, and Reliability Issues
Introduction
Welcome (PDF)
Michael Nicolaidis, iRoC Technologies, France
Lorena Anghel, TIMA, France
Cecilia Metra, University of Bologna, Italy
Kaushik Roy, Purdue University, USA
pp. x
Keynote
null
Session 1: Transient Fault Modeling and Analysis
null
A. Douin, Universit? Bordeaux 1
V. Pouget, Universit? Bordeaux 1
D. Lewis, Universit? Bordeaux 1
P. Fouillat, Universit? Bordeaux 1
P. Perdu, CNES
pp. 9-13
P. Gawkowski, Warsaw University of Technology
J. Sosnowski, Warsaw University of Technology
B. Radko, Warsaw University of Technology
pp. 14-19
Session 2: Transient Faults' Hardening Techniques
null
J. M. Cazeaux, University of Bologna
D. Rossi, University of Bologna
M. Omaña, University of Bologna
C. Metra, University of Bologna
A. Chatterjee, Georgia Institute of Technology
pp. 23-28
Cristiano Lazzari, Institute National Polytechnique de Grenoble
Lorena Anghel, Institute National Polytechnique de Grenoble
Ricardo A. L. Reis, Universidade Federal do Rio Grande do Sul
pp. 29-34
Yuvraj S. Dhillon, Georgia Institute of Technology
Abdulkadir U. Diril, Georgia Institute of Technology
Abhijit Chatterjee, Georgia Institute of Technology
Cecilia Metra, University of Bologna
pp. 35-40
Session 3: SEU Effects in FPGAs
null
Celia L?pez-Ongil, Carlos III University of Madrid
Mario Garc?a-Valderas, Carlos III University of Madrid
Marta Portela-Garc?, Carlos III University of Madrid
Luis Entrena-Arrontes, Carlos III University of Madrid
pp. 43-48
M. Alderighi, IASF, INAF
F. Casini, Sanitas EG, s.r.l.
S. D'Angelo, IASF, INAF
M. Mancini, IASF, INAF
A. Paccagnella, Universit? of Padova
S. Pastore, Sanitas EG, s.r.l.
G. R. Sechi, IASF, INAF
pp. 49-53
Special Session 1: Robust Design Techniques for Soft Errors
null
Y. Zorian, Virage Logic Corporation
V. A. Vardanian, Virage Logic Yerevan Branch
K. Aleksanyan, Virage Logic Yerevan Branch
K. Amirkhanyan, Virage Logic Yerevan Branch
pp. 63-68
T. M. Mak, Intel Corporation
Subhasish Mitra, Intel Corporation
Ming Zhang, Intel Corporation
pp. 69
Special Session 2: Simulation and Mitigation of Single Event Effects
null
G. Hubert, EADS, Corporate Research Center
N. Buard, EADS, Corporate Research Center
C. Weulersse, EADS, Corporate Research Center
T. Carriere, EADS, Space Transportation
M.-C. Palau, EADS, Space Transportation
J.-M. Palau, University of Montpellier
D. Lambert, CEA/DAM
J. Baggio, CEA/DAM
F. Wrobel, University of Nice
F. Saigne, University of Montpellier
R. Gaillard, NFODUC
pp. 87-94
Special Session 3: Self Calibrating Design
null
Chris H. Kim, University of Minnesota
Steven Hsu, Intel Corporation, Purdue University
Ram Krishnamurthy, Intel Corporation, Purdue University
Shekhar Borkar, Intel Corporation, Purdue University
Kaushik Roy, Intel Corporation, Purdue University
pp. 100-105
Donghoon Han, Georgia Institute of Technology
Selim Sermet Akbay, Georgia Institute of Technology
S. Bhattacharya, Georgia Institute of Technology
A. Chatterjee, Georgia Institute of Technology
William R. Eisenstadt, University of Florida
pp. 106-111
Special Session 4: Secure Implementations
null
Lejla Batina, Katholieke Universiteit Leuven
Nele Mentens, Katholieke Universiteit Leuven
Ingrid Verbauwhede, Katholieke Universiteit Leuven
pp. 118-121
Session 4: On-Line Testing for Secure and Asynchronous Chips
null
D. Shang, University of Newcastle upon Tyne
A. Bystrov, University of Newcastle upon Tyne
A. Yakovlev, University of Newcastle upon Tyne
D. Koppad, University of Newcastle upon Tyne
pp. 135-140
Session 5: Self Checking Strategies
null
S. Matakias, University of Athens
Y. Tsiatouhas, University of Ioannina
Th. Haniotakis, Southern Illinois University
A. Arapoyanni, University of Athens
A. Efthymiou, University of Athens
pp. 149-156
Julian Murphy, University of Newcastle upon Tyne
Alex Bystrov, University of Newcastle upon Tyne
Alex Yakovlev, University of Newcastle upon Tyne
pp. 157-162
Session 6: Process Variations, Leakage, and Power Supply Noise Detection and Tolerance
null
B. Alorda, Université des les Illes Balears
S. Bota, Université des les Illes Balears
J. Segura, Université des les Illes Balears
pp. 177-182
André K. Nieuwland, Philips Research Laboratories
Atul Katoch, Philips Research Laboratories
Daniele Rossi, University of Bologna
Cecilia Metra, University of Bologna
pp. 183-189
Session 7: Posters
null
Damien Leroy, iRoC Technologies SA
Stanisław J. Piestrak, University of Metz
Fabrice Monteiro, University of Metz
Abbas Dandache, University of Metz
pp. 193-194
G. C. Cardarilli, University of Rome "Tor Vergata"
S. Pontarelli, University of Rome "Tor Vergata"
M. Re, University of Rome "Tor Vergata"
A. Salsano, University of Rome "Tor Vergata"
pp. 201-202
F. Vargas, Catholic University - PUCRS
D. L. Cavalcante, Catholic University - PUCRS
E. Gatti, Instituto Nacional de Tecnologia Industrial
D. Prestes, Catholic University - PUCRS
D. Lupi, Instituto Nacional de Tecnologia Industrial
pp. 207-208
Panel
null
Regis Leveugle, Tima Laboratory
Yervant Zorian, Virage Logic
L. Breveglieri, Politechnic di Milano
R. Leveugle, TIMA Laboratory
A. Nieuwland, Philips
K. Rothbart, Technical University of Graz
J. P. Seifert, Intel Inc.
pp. 211
Session 8: Testing Issues
null
I. Voyiatzis, Technological Educational Institute of Athens
D. Gizopoulos, University of Piraeus
A. Paschalis, University of Athens
pp. 215-220
G. Xenoulis, University of Piraeus
M. Psarakis, University of Piraeus
D. Gizopoulos, University of Piraeus
A. Paschalis, University of Athens
pp. 227-232
Session 9: SoC Testing and Fault Tolerance
null
A. Manzone, Centro Ricerche Fiat
P. Bernardi, Politecnico di Torino
M. Grosso, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
E. Sanchez, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
pp. 235-240
R. Kothe, Brandenburg University of Technology Cottbus
C. Galke, Brandenburg University of Technology Cottbus
H. T. Vierhaus, Brandenburg University of Technology Cottbus
pp. 241-246
Session 10: Multiple Bit Upset Evaluation and Correction
null
Erik Sch?, Universidade Federal do Rio Grande do Sul
Luigi Carro, Universidade Federal do Rio Grande do Sul
pp. 255-259
Balkaran Gill, Case Western Reserve University
Michael Nicolaidis, IROC Technologies
Chris Papachristou, Case Western Reserve University
pp. 266-271
null
Special Session 5: Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing
null
Author Index
Author Index (PDF)
pp. 325-326
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