A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory

Andrzej Krasniewski

doi:10.1109/IOLTS.2005.11

I
IOLTS
2005
11th IEEE International On-Line Testing Symposium
Abstract - A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory

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11th IEEE International On-Line Testing Symposium

A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory (PDF)

Saint Raphael, French Riviera, France

July 06-July 08

ISBN: 0-7695-2406-0

	ASCII Text	x
	Andrzej Krasniewski, "A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory," 11th IEEE International On-Line Testing Symposium, pp. 197-198, 11th IEEE International On-Line Testing Symposium, 2005.

	BibTex	x
	@article{ 10.1109/IOLTS.2005.11, author = {Andrzej Krasniewski}, title = {A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory}, journal ={11th IEEE International On-Line Testing Symposium}, volume = {0}, year = {2005}, issn = {1530-1591}, pages = {197-198}, doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.11}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - 11th IEEE International On-Line Testing Symposium TI - A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory SN - 1530-1591 SP197 EP198 A1 - Andrzej Krasniewski, PY - 2005 KW - null VL - 0 JA - 11th IEEE International On-Line Testing Symposium ER -

Andrzej Krasniewski, Warsaw University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.11

We present several low-cost concurrent error detection schemes for a sequential circuit implemented using FPGAs with embedded memory blocks. The experimental results show that for many of the examined circuits, a reasonable level of error detection can be obtained at the circuitry overhead of less than 10% - a level recommended by proponents of a "pragmatic" approach to on-line testing.

Citation:

Andrzej Krasniewski, "A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory," iolts, pp.197-198, 11th IEEE International On-Line Testing Symposium, 2005

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