CSDL - Proceedings I

Organizing Committee (PDF)

pp. xii

Program Committee (PDF)

pp. xiii

TTTC Information (PDF)

pp. 227

Welcome Message

null

Opening Session-Keynote Talks

null

Challenges and Opportunities for FPGA Programmable System Platforms (PDF)

Ivo Bolsens, Xilinx

pp. 3

Technology Scaling Trends and Accelerated Testing for Soft Errors in Commercial Silicon Devices (PDF)

null

Robert Baumann, Texas Instruments

pp. 4

Session 1: On-Line Testing Approaches

null

Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC (Abstract)

Yi Zhao, University of California, San Diego

Sujit Dey, University of California, San Diego

pp. 7

PDF

A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs (Abstract)

Y. Tsiatouhas, University of Ioannina

S. Matakias, University of Athens

A. Arapoyanni, University of Athens

Th. Haniotakis, Southern Illinois University

pp. 12

PDF

On-Line Error Detecting Constant Delay Adder (Abstract)

Whitney J. Townsend, The University of Texas at Austin

Jacob A. Abraham, The University of Texas at Austin

Parag K. Lala, University of Arkansas

pp. 17

PDF

Session 2: Self Checking Circuits

null

A Modulo p Checked Self-Checking Carry Select Adder (Abstract)

V. Ocheretnij, University of Potsdam

M. G?ssel, University of Potsdam

E. S. Sogomonyan, University of Potsdam

D. Marienfeld, University of Potsdam

pp. 25

PDF

Foundation of Combined Datapath and Controller Self-checking Design (Abstract)

Petros Oikonomakos, University of Southampton

Mark Zwolinski, University of Southampton

pp. 30

PDF

Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits (Abstract)

Kartik Mohanramy, University of Texas at Austin

Egor S. Sogomonyanz, University of Potsdam

Michael G.osselz, University of Potsdam

Nur A. Toubay, University of Texas at Austin

pp. 35

PDF

Session 3: Checker Designs

null

A Design Method for Embedded Self-Testing t-UED and BUED Code Checkers (Abstract)

Steffen Tarnick, SATCON GmbH

pp. 43

PDF

Designing FPGA based Self-Testing Checkers for m-out-of-n Codes (Abstract)

A. Matrosova, Tomsk State University, Russia

V. Ostrovsky, Tel Aviv University, Israel

I. Levin, Tel Aviv University, Israel

K. Nikitin, Tomsk State University, Russia

pp. 49

PDF

An Analog Checker With Input-Relative Tolerance for Duplicate Signals (Abstract)

Haralampos-G. D. Stratigopoulos, Yale University

Yiorgos Makris, Yale University

pp. 54

PDF

Session 4: Fault Tolerance

null

Power Consumption of Fault Tolerant Codes: the Active Elements (Abstract)

D. Rossi, University of Bologna

V.E.S. van Dijk, Philips Research Laboratories

R.P. Kleihorst, Philips Research Laboratories

A.K. Nieuwland, Philips Research Laboratories

C. Metra, University of Bologna

pp. 61

PDF

On the Probability of Detecting Data Errors Generated by Permanent Faults Using Time Redundancy (Abstract)

Joakim Aidemark, Chalmers University of Technology

Peter Folkesson, Chalmers University of Technology

Johan Karlsson, Chalmers University of Technology

pp. 68

PDF

The positive effect on IC yield of embedded Fault Tolerance for SEUs (Abstract)

Andr? K. Nieuwland, Philips Research Laboratories

Richard P. Kleihorst, Philips Research Laboratories

pp. 75

PDF

Panel Session 1: How Can Defect-Based Test Be Made to Work in a Foundry World?

null

Session 5: Built In Self Test and Self Repair

null

On-Line Testable Decimation Filter Design for AMS Systems (Abstract)

M. A. Naal, TIMA Laboratory

E. Simeu, TIMA Laboratory

S. Mir, TIMA Laboratory

pp. 83

PDF

An Efficient BIST scheme for High-Speed Adders (Abstract)

D. G. Nikolos, University of Partas

D. Nikolos, University of Partas; Computer Technology Institute

H. T. Vergos, University of Partas; Computer Technology Institute

C. Efstathiou, TEI of Athens

pp. 89

PDF

Memory Built-In Self-Repair for Nanotechnologies (Abstract)

M. Nicolaidis, iRoC Technologies

N. Achouri, iRoC Technologies

L. Anghel, TIMA laboratory

pp. 94

PDF

Session 6: Analysis and Modelling of Transient and Delay Faults

null

Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits (Abstract)

M. Sonza Reorda, Politecnico di Torino

M. Violante, Politecnico di Torino

pp. 101

PDF

An Improved Markov Source Design for Scan BIST (Abstract)

Chaowen Yu, University of Iowa

Wei Li, University of Iowa

Sudhakar M. Reddy, University of Iowa

Irith Pomeranz, Purdue University

pp. 106

PDF

A Model for Transient Fault Propagation in Combinatorial Logic (Abstract)

Martin Oma?, University of Bologna

Giacinto Papasso, University of Bologna

Daniele Rossi, University of Bologna

Cecilia Metra, University of Bologna

pp. 111

PDF

Session 7: Analysis and Verification of FPGA Faults

null

Analyzing SEU Effects in SRAM-based FPGAs (Abstract)

M. Violante, Politecnico di Torino

M. Ceschia, Universit? di Padova; Istituto Nazionale di Fisica Nucleare

M. Sonza Reorda, Politecnico di Torino

A. Paccagnella, Universit? di Padova; Istituto Nazionale di Fisica Nucleare

P. Bernardi, Politecnico di Torino

M. Rebaudengo, Politecnico di Torino

D. Bortolato, Universit? di Padova

M. Bellato, Istituto Nazionale di Fisica Nucleare

P. Zambolin, Universit? di Padova

A. Candelori, Istituto Nazionale di Fisica Nucleare

pp. 119

PDF

Defect Analysis for Delay-Fault BIST in FPGAs (Abstract)

P. Girard, Universit? Montpellier II / CNRS

O. H?ron, Universit? Montpellier II / CNRS

S. Pravossoudovitch, Universit? Montpellier II / CNRS

M. Renovell, Universit? Montpellier II / CNRS

pp. 124

PDF

A Fault Injection Tool for SRAM-based FPGAs (Abstract)

M. Alderighi, Istituto di Astrofisica Spaziale e Fisica Cosmica

S. D'Angelo, Istituto di Astrofisica Spaziale e Fisica Cosmica

M. Mancini, Istituto di Astrofisica Spaziale e Fisica Cosmica

G. R. Sechi, Istituto di Astrofisica Spaziale e Fisica Cosmica

pp. 129

PDF

Session 8: On-Line Testing of Microprocessor-Based Systems

null

Low-Cost On-Line Fault Detection Using Control Flow Assertions (Abstract)

Rajesh Venkatasubramanian, University of Michigan

John P. Hayes, University of Michigan

Brian T. Murray, Brighton Technical Center

pp. 137

PDF

A Watchdog Processor to Detect Data and Control Flow Errors (Abstract)

Alfredo Benso, Politecnico di Torino

Stefano Di Carlo, Politecnico di Torino

Giorgio Di Natale, Politecnico di Torino

Paolo Prinetto, Politecnico di Torino

pp. 144

PDF

Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores (Abstract)

G. Xenoulis, University of Piraeus, Greece

D. Gizopoulos, University of Piraeus, Greece

N. Kranitis, University of Athens, Greece

A. Paschalis, University of Athens, Greece

pp. 149

PDF

Session 9: Posters

null

On Compaction-Based Concurrent Error Detection (PDF)

Sobeeh Almukhaizim, Yale University

Petros Drineas, Rensselaer Polytechnic Institute

Yiorgos Makris, Yale University

pp. 157

Increasing Implementability of \beta-driven Threshold Checkers (PDF)

V. Varshavsky, NNT Israel

I. Levin, Tel Aviv University Israel

V. Ostrovsky, Tel Aviv University Israel

pp. 158

An RT-level Concurrent Error Detection Technique for Data Dominated Systems (PDF)

O. Goloubeva, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

M. Violante, Politecnico di Torino

pp. 159

FAUST: FAUlt-injection Script-based Tool (PDF)

A. Benso, Politecnico di Torino

S. Di Carlo, Politecnico di Torino

G. Di Natale, Politecnico di Torino

P. Prinetto, Politecnico di Torino

I. Solcia, Politecnico di Torino

L. Tagliaferri, Politecnico di Torino

pp. 160

Fault Injection in Digital Logic Circuits at the VHDL Level (PDF)

S. R. Seward, University of Arkansas

P. K. Lala, University of Arkansas

pp. 161

Radiation test methodology for SRAM-based FPGAs by using THESIC+ (PDF)

M. Alderighi, Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR

F. Casini, Sanitas EG S.R.L.

S. D'Angelo, Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR

F. Faure, TIMA Laboratory

M. Mancini, Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR

S. Pastore, Sanitas EG S.R.L.

G. R. Sechi, Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR

R. Velazco, TIMA Laboratory

pp. 162

Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy? (PDF)

F. Vargas, Catholic University - PUCRS

D. Brum, Catholic University - PUCRS

D. Prestes, Catholic University - PUCRS

L. Bolzani, Catholic University - PUCRS

E. Rhod, Catholic University - PUCRS

M. Reorda, Politecnico di Torino

pp. 163

Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems (PDF)

F. M. Gon?alves, IST/INESC-ID

M. B. Santos, IST/INESC-ID

I. C. Teixeira, IST/INESC-ID

J. P. Teixeira, IST/INESC-ID

pp. 164

Analysis of Bit Transition Count for EDAC Encoded FSM (PDF)

N. Venkateswaran, WAran Research Foundation, India

V. Balaji, Sri Venkateswara College of Engineering, India

V. Mahalingam, Sri Venkateswara College of Engineering, India

T. L. Rajaprabhu, Sri Venkateswara College of Engineering, India

pp. 166

A Configurable Built in Current Sensor for Mixed Signal Circuit Testing (PDF)

Rodrigo Picos, Universitat Illes Balears

Joan Font, Universitat Illes Balears

Eugeni Isern, Universitat Illes Balears

Miquel Roca, Universitat Illes Balears

Eugenio Garc?, Universitat Illes Balears

pp. 167

Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption (Abstract)

Andrzej Krasniewski, Warsaw University of Technology

pp. 168

PDF

Session 10: Merging On-Line and Off-Line Testing

null

Control Signal Protection For High Performance Processors (Abstract)

M. Pflanz, IBM Deutschland Entwicklung GmbH, Germany

H. T. Vierhaus, Brandenburg TU Cottbus, Germany

pp. 173

PDF

An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing (Abstract)

B. Alorda, Univ. de les Illes Balears

J. Segura, Univ. de les Illes Balears

pp. 178

PDF

Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip (Abstract)

Christian Galke, Brandenburg University of Technology Cottbus

Marcus Grabow, Brandenburg University of Technology Cottbus

Heinrich Theodor Vierhaus, Brandenburg University of Technology Cottbus

pp. 183

PDF

Panel Session 2: When Will Soft Errors Become A Design Constraint?

null

Session 11: Industrial Application Cases

null

On a Redundant Diversified Steering Angle Sensor (Abstract)

Elmar Dilger, Robert Bosch GmbH

Matthias Gulbins, Fraunhofer-Institut f?r Integrierte Schaltungen

Thomas Ohnesorge, Fraunhofer-Institut f?r Integrierte Schaltungen

Bernd Straube, Fraunhofer-Institut f?r Integrierte Schaltungen

pp. 191

PDF

Automatic toolset for fault tolerant design: results demonstration on a running industrial application (Abstract)

Alberto Manzone, Centro Ricerche FIAT

Claudio Genta, Centro Ricerche FIAT

pp. 197

PDF

Error-Injection-Based Failure Characterization of the IEEE 1394 Bus (Abstract)

D. J. Beauregard, University of Illinois at Urbana-Champaign

Z. Kalbarczyk, University of Illinois at Urbana-Champaign

R. K. Iyer, University of Illinois at Urbana-Champaign

S. Chau, National Aeronautics and Space Administration

L. Alkalai, National Aeronautics and Space Administration

pp. 202

PDF

Session 12: Advanced Testing and Repair Issues

null

A Methodology for Test Replacement Solutions of Obsolete Processors (Abstract)

R. Velazco, TIMA Laboratory

L. Anghel, TIMA Laboratory

S. Saleh, TIMA Laboratory

pp. 209

PDF

Crosstalk Effect Minimization for Encoded Busses (Abstract)

L. Di Silvio, D.E.I.S. University of Bologna

D. Rossi, D.E.I.S. University of Bologna

C. Metra, D.E.I.S. University of Bologna

pp. 214

PDF

InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs (Abstract)

Dimitri Kagaris, Southern Illinois University

Spyros Tragoudas, Southern Illinois University

pp. 219

PDF

Author's Index (PDF)

pp. 225