CSDL - Proceedings I

Message from the Program Chair (PDF)

pp. viii

Workshop Committee (PDF)

pp. ix

Keynote Speaker

Session 1: Effectiveness of IDDQ Testing: Session Chair: Jerry Soden, Sandia National Labs

Realistic Coverages of Voltage and Current Tests (Abstract)

Frank Peters, Eindhoven University of Technology

Steven Oostdijk, Philips Electronic Design & Tools

pp. 4

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The Effectiveness of IDDQ and High Voltage Stress for Burn-in Elimination (Abstract)

Rinya Kawahara, LSI Division, Kawasaki-steel Inc.

Osamu Nakayama, LSI Division, Kawasaki-steel Inc.

Tatsuru Kurasawa, LSI Division, Kawasaki-steel Inc.

pp. 9

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Evaluation of Early Failure Screening Methods (Abstract)

Terry Barrette, LSI Logic Corporation

Vishwas Bhide, LSI Logic Corporation

Kaushik De, LSI Logic Corporation

Mike Stover, LSI Logic Corporation

Emery Sugasawara, LSI Logic Corporation

pp. 14

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Session 2: Testing and Testability: Session Chair: Sankaran Menon, South Dakota School of Mines & Technology

Improving Bridge-Fault Testability and Confidence of IDDQ Testing through Circuit Placement (Abstract)

Nikhil Sharma, Synopsys Inc.

C.P. Ravikumar, Indian Institute of Technology

pp. 20

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Current Signatures for Production Testing (Abstract)

Anne E. Gattiker, Carnegie Mellon University

Wojciech Maly, Carnegie Mellon University

Phil Nigh, IBM Microelectronics Division

Dale Grosch, IBM Microelectronics Division

pp. 25

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IDDQ Testability of Flip-flop Structures (Abstract)

Hiroshi Yamazaki, Tokyo Metropolitan University

Yukiya Miura, Tokyo Metropolitan University

pp. 29

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Session 3: Limit Setting and Testing: Session Chair: Joel Ferguson, University of California, Santa Cruz

Test of CMOS Circuits Based on its Energy Consumption (Abstract)

M.A. Ortega, Universitat Politecnica de Catalunya

J. Rius, Universitat Politecnica de Catalunya

J. Figueras, Universitat Politecnica de Catalunya

pp. 36

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Standard Cell Library Characterization for Setting Current Limits for IDDQ Testing (Abstract)

Steven D. Millman, Motorola

John M. Acken, Terret, Inc.

pp. 41

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SHOrt Voltage Elevation (SHOVE) Testing (Abstract)

Jonathan T.-Y. Chang, Stanford University

Edward J. McCluskey, Stanford University

pp. 45

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Low Cost Test Solution for IDDQ (Abstract)

Bob Thomas, Cadence Design Systems, Inc.

Rick Andlauer, Cadence Design Systems, Inc.

pp. 50

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Session 4: Current Sensors: Session Chair: Kenneth Butler, Texas Instruments

A Fast and Sensitive Built-in Current Sensor for IDDQ Testing (Abstract)

Chih-Wen Lu, National Chiao Tung University

Chung-Len Lee, National Chiao Tung University

Jwu-E Chen, Chung-Hwa Polytechnic

pp. 56

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Implementation of a BIC Monitor in a New Analog BIST Structure. (Abstract)

M. Sidiropulos, Technical University of Brno

V. Stopjakova, Slovak Technical University

H. Manhaeve, KHBO

pp. 59

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On Chip IDDX Sensor (Abstract)

Yvan Maidon, Universite Bordeaux I

Yann Deval, Universite Bordeaux I

Pascal Fouillat, Universite Bordeaux I

Jean Tomas, Universite Bordeaux I

Jean Paul Dom, Universite Bordeaux I

pp. 64

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Feasibility of Employing and IDDQ Output Amplifier in Deep Submicron Built-in Current Sensors (Abstract)

Stephan P. Athan, University of South Florida

David L. Landis, Penn State University

pp. 68

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Session 5: Test Generation and Testing: Session Chair: Rob Roy, NEC

An Efficient IDDQ Test Generation Scheme for Bridging Faults in CMOS Digital Circuits (Abstract)

Tzuhao Chen, University of Illinois

Ibrahim N. Hajj, University of Illinois

Elizabeth M. Rudnick, University of Illinois

Janak H. Patel, University of Illinois

pp. 74

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Equivalence fault collapsing for transistor leakage faults (Abstract)

Wen Xiaoqing, Dept. of Inf. Eng., Akita Univ., Japan

K.K. Saluja, Dept. of Inf. Eng., Akita Univ., Japan

K. Kinoshita, Dept. of Inf. Eng., Akita Univ., Japan

H. Tamamoto, Dept. of Inf. Eng., Akita Univ., Japan

pp. 79

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Testing the realistic bridging faults in CMOS circuits (Abstract)

Peilin Song, Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA

Jien-Chung Lo, Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA

pp. 84

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Semi-digital off-chip I/sub DDQ/ monitor developments: towards a general-purpose digital current monitor (Abstract)

H. Manhaeve, Dept. of Microelectron., KHBO, Ostend, Belgium

M. Svajda, Dept. of Microelectron., KHBO, Ostend, Belgium

B. Straka, Dept. of Microelectron., KHBO, Ostend, Belgium

pp. 89

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Automatic Test Pattern Generation for IDDQ Faults Based upon Symbolic Simulation (Abstract)

Lluis Ribas-Xirgo, Microelectronics Group Universitat Aut\`onoma de Barcelona

Jordi Carrabina-Bordoll, Microelectronics Group Universitat Aut\`onoma de Barcelona

pp. 94

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Panel Session: Where Should IDDQ R&D Be Directed in 1997?

Panel Chair: Peter Maxwell, Hewlett-Packard

Position Papers

Some faults need an I/sub ddq/ test (PDF)

S.R. Makar, Center for Reliable Comput., Stanford Univ., CA, USA

E.J. McCluskey, Center for Reliable Comput., Stanford Univ., CA, USA

pp. 102

Author Index (PDF)

pp. 105