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2009 International Conference on Parallel Processing Workshops
System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance
Vienna, Austria
September 22-September 25
ISBN: 978-0-7695-3803-7
| ASCII Text | x | ||
| Vahid Lari, Frank Hannig, Jürgen Teich, "System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance," 2012 41st International Conference on Parallel Processing Workshops, pp. 528-534, 2009 International Conference on Parallel Processing Workshops, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/ICPPW.2009.72, author = {Vahid Lari and Frank Hannig and Jürgen Teich}, title = {System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance}, journal ={2012 41st International Conference on Parallel Processing Workshops}, volume = {0}, year = {2009}, issn = {1530-2016}, pages = {528-534}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICPPW.2009.72}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 41st International Conference on Parallel Processing Workshops TI - System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance SN - 1530-2016 SP528 EP534 A1 - Vahid Lari, A1 - Frank Hannig, A1 - Jürgen Teich, PY - 2009 KW - System-on-a-chip KW - System performance evaluation KW - Double buffering mechanism KW - Virtual system prototyping KW - Coarse-grained reconfigurable architectures VL - 0 JA - 2012 41st International Conference on Parallel Processing Workshops ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICPPW.2009.72
This paper studies the loosely integration of application accelerators consisting of an array of tightly-coupled lightweight reconfigurable processors into a system-on-a-chip. In order to explore a multitude of design variations a C++ simulation model of the accelerator has been integrated with a system-on-a-chip environment consisting of a general purpose processor, a DMA controller, an interrupt controller and a memory module. Dependent on the applications, different kinds of I/O buffers are designed around the processor array and the effects of the buffer size on the overall execution time are evaluated. The evaluations are based on new mathematical estimation models derived from the system and application constraints. The estimations are validated with experimental results with an error less than 1\%. Exploring several designs points that using our architecture along with suitable buffer sizes, can improve the system execution time, one to two magnitudes for the selected algorithms.
Index Terms:
System-on-a-chip, System performance evaluation, Double buffering mechanism, Virtual system prototyping, Coarse-grained reconfigurable architectures
Citation:
Vahid Lari, Frank Hannig, Jürgen Teich, "System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance," icppw, pp.528-534, 2009 International Conference on Parallel Processing Workshops, 2009
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