This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
2007 International Conference on Parallel Processing (ICPP 2007)
Performance Improvement Methodology for ClearSpeed?s CSX600
Xi'an, China
September 10-September 14
ISBN: 0-7695-2933-X
ASCII Text
x 
 
Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano, "Performance Improvement Methodology for ClearSpeed?s CSX600," 2012 41st International Conference on Parallel Processing, pp. 77, 2007 International Conference on Parallel Processing (ICPP 2007), 2007.
 
 
BibTex
x
 
@article{ 10.1109/ICPP.2007.66,
author = {Yuri Nishikawa and Michihiro Koibuchi and Masato Yoshimi and Kenichi Miura and Hideharu Amano},
title = {Performance Improvement Methodology for ClearSpeed?s CSX600},
journal ={2012 41st International Conference on Parallel Processing},
volume = {0},
year = {2007},
issn = {0190-3918},
pages = {77},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICPP.2007.66},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - 2012 41st International Conference on Parallel Processing
TI - Performance Improvement Methodology for ClearSpeed?s CSX600
SN - 0190-3918
SP
EP
A1 - Yuri Nishikawa,
A1 - Michihiro Koibuchi,
A1 - Masato Yoshimi,
A1 - Kenichi Miura,
A1 - Hideharu Amano,
PY - 2007
KW - null
VL - 0
JA - 2012 41st International Conference on Parallel Processing
ER -
 
Yuri Nishikawa, Keio University, Japan
Michihiro Koibuchi, National Institute of Informatics, Japan
Masato Yoshimi, Keio University, Japan
Kenichi Miura, National Institute of Informatics, Japan
Hideharu Amano, Keio University, Japan
This paper focuses on a performance of network-on-achip (NoC) and I/O of ClearSpeed?s CSX600 coprocessor with 96 multithread processing elements. Two versions of the Himeno Benchmark were implemented on the CSX600 to evaluate its performance when it encounters frequent memory transfers between shared and local memories, or between local memories. In order to efficiently use the NoC bandwidth, the dataflow was customized to the one-dimensional array structure of CSX600?s NoC . The results of evaluation and profiling indicate that the performance was lower than 1/50 of the sustained performance. We show three key points to improve the performance on such a case: 1) exploiting bandwidth between mono and poly memory, 2) further program tuning, and 3) architectural reform.
Citation:
Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano, "Performance Improvement Methodology for ClearSpeed?s CSX600," icpp, pp.77, 2007 International Conference on Parallel Processing (ICPP 2007), 2007
Usage of this product signifies your acceptance of the Terms of Use.