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1996 International Conference on Parallel Processing (ICPP'96) - Volume 1
(R) Equivalence Between SP2 High Performance Switches and Three-Stage Clos Networks
Bloomington, IL
August 12-August 16
ISBN: 0-8186-7623-x
ASCII Text
x 
 
M. ten Bruggencate, S. Chalasani, "(R) Equivalence Between SP2 High Performance Switches and Three-Stage Clos Networks," 2012 41st International Conference on Parallel Processing, vol. 1, pp. 0001, 1996 International Conference on Parallel Processing (ICPP'96) - Volume 1, 1996.
 
 
BibTex
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@article{ 10.1109/ICPP.1996.537136,
author = {M. ten Bruggencate and S. Chalasani},
title = {(R) Equivalence Between SP2 High Performance Switches and Three-Stage Clos Networks},
journal ={2012 41st International Conference on Parallel Processing},
volume = {1},
year = {1996},
isbn = {0-8186-7623-x},
pages = {0001},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICPP.1996.537136},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - 2012 41st International Conference on Parallel Processing
TI - (R) Equivalence Between SP2 High Performance Switches and Three-Stage Clos Networks
SN - 0-8186-7623-x
SP
EP
A1 - M. ten Bruggencate,
A1 - S. Chalasani,
PY - 1996
KW - multiprocessor interconnection networks; performance evaluation; parallel architectures; functional equivalence; SP2 switches; three-stage Clos networks; routing communications; distributed control algorithm; linear-complement permutations
VL - 1
JA - 2012 41st International Conference on Parallel Processing
ER -
 
M. ten Bruggencate, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
S. Chalasani, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Abstract: In this paper we prove the functional equivalence of SP2 switches and rearrangeable three-stage Clos networks. From this equality we derive results on routing communications in SP2 switches. The present an algorithm using centralized control which can route any permutation in one pass through SP2 switches, for various system sizes. Further, we present a distributed control algorithm which can route the important class of linear-complement permutations through SP2 switches. Our results not only highlight the capabilities of SP2 switches, but also demonstrate how to efficiently route permutations at the application level.
Index Terms:
multiprocessor interconnection networks; performance evaluation; parallel architectures; functional equivalence; SP2 switches; three-stage Clos networks; routing communications; distributed control algorithm; linear-complement permutations
Citation:
M. ten Bruggencate, S. Chalasani, "(R) Equivalence Between SP2 High Performance Switches and Three-Stage Clos Networks," icpp, vol. 1, pp.0001, 1996 International Conference on Parallel Processing (ICPP'96) - Volume 1, 1996
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