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International Conference on Networking, International Conference on Systems and International Conference on Mobile Communications and Learning Technologies (ICNICONSMCL'06)
A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers
Morne, Mauritius
April 23-April 29
ISBN: 0-7695-2552-0
| ASCII Text | x | ||
| Asim J. Al-Khalili, "A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers," Mobile Communications and Learning Technologies, Conference on Networking, Conference on Systems, International Conference on, pp. 183, International Conference on Networking, International Conference on Systems and International Conference on Mobile Communications and Learning Technologies (ICNICONSMCL'06), 2006. | |||
| BibTex | x | ||
| @article{ 10.1109/ICNICONSMCL.2006.2, author = {Asim J. Al-Khalili}, title = {A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers}, journal ={Mobile Communications and Learning Technologies, Conference on Networking, Conference on Systems, International Conference on}, volume = {0}, year = {2006}, isbn = {0-7695-2552-0}, pages = {183}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICNICONSMCL.2006.2}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Mobile Communications and Learning Technologies, Conference on Networking, Conference on Systems, International Conference on TI - A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers SN - 0-7695-2552-0 SP EP A1 - Asim J. Al-Khalili, PY - 2006 KW - null VL - 0 JA - Mobile Communications and Learning Technologies, Conference on Networking, Conference on Systems, International Conference on ER - | |||
A new method for generating a square of a signed binary number is given. The method is shown to outperform other methods found in literature. Results of comparison with other methods through direct synthesis using FPGA is given. Methods to optimize the architecture in terms of delay, area, power or any combination of these is presented. A C++ program is written that generates VHDL code for any given binary number. A variety of scalable, optimized and portable output is possible by selecting the optimization criteria as delay, power or area.
Citation:
Asim J. Al-Khalili, "A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers," icniconsmcl, pp.183, International Conference on Networking, International Conference on Systems and International Conference on Mobile Communications and Learning Technologies (ICNICONSMCL'06), 2006
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