Paris, France France
July 18, 2012 to July 20, 2012
Modeling and verifying complex real-time systems, involving timing delays, are notoriously difficult problems. Checking the correctness of a system for one particular value for each delay does not give any information for other values. It is hence interesting to reason parametrically, by considering that the delays are parameters (unknown constants) and synthesize a constraint guaranteeing a correct behavior. We present here Parametric Stateful Timed CSP, a language capable of specifying hierarchical real-time systems with complex data structures. Although we prove that the synthesis is undecidable in general, we present an algorithm for efficient parameter synthesis that behaves well in practice.
Clocks, Delay, Cost accounting, Semantics, Real time systems, Reactive power, refinement, CSP, parametric timed verification, model checking, robustness
Etienne Andre, Yang Liu, Jun Sun, Jin-Song Dong, "Parameter Synthesis for Hierarchical Concurrent Real-Time Systems", ICECCS, 2012, Engineering of Complex Computer Systems, IEEE International Conference on, Engineering of Complex Computer Systems, IEEE International Conference on 2012, pp. 253-262, doi:10.1109/ICECCS.2012.29