Mar. 5, 2007 to Mar. 7, 2007
Dipnarayan Guha , Nanyang Technological University, Singapore
The abstract is to be in fully-justified italicized text, at the top of the left-hand column as it is here, below the author information. Designing a reconfigurable frame parser to translate radio protocol descriptions to asynchronous microprocessor cores is a relatively recent concept. As asynchronous microprocessors do not run an operating system, the paradigm of multi-radio support on these cores need to be investigated in a different light than the conventional Software Defined Radios. The main challenge in such a design is realizing multi-radio FFD (fully functional device) emulation on an extremely low-memory footprint before translating it to the asynchronous core. In this work-in-progress paper, we describe some of the design methodologies involved in designing a reconfigurable radio MAC frame parser for translating multi-radio protocol description to asynchronous processor cores. We intend to realize this run-time in hardware and are working to realize a prototype on FPGA. The prototype would demonstrate a design methodology to include asynchronous instruction set targets in dynamic run-time multi-language compiler translation.
Dipnarayan Guha, "Reconfigurable Frame Parser Design for Multi-Radio Support on Asynchronous Microprocessor Cores", ICCTA, 2007, International Conference on Computing: Theory and Applications, International Conference on Computing: Theory and Applications 2007, pp. 122-127, doi:10.1109/ICCTA.2007.110