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2005 International Conference on Computer Design
Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz
San Jose, California
October 02-October 05
ISBN: 0-7695-2451-6
| ASCII Text | x | ||
| Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng, "Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz," 2012 IEEE 30th International Conference on Computer Design (ICCD), pp. 111-118, 2005 International Conference on Computer Design, 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/ICCD.2005.84, author = {Yuanfang Hu and Hongyu Chen and Yi Zhu and Andrew A. Chien and Chung-Kuan Cheng}, title = {Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz}, journal ={2012 IEEE 30th International Conference on Computer Design (ICCD)}, volume = {0}, year = {2005}, isbn = {0-7695-2451-6}, pages = {111-118}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.84}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE 30th International Conference on Computer Design (ICCD) TI - Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz SN - 0-7695-2451-6 SP111 EP118 A1 - Yuanfang Hu, A1 - Hongyu Chen, A1 - Yi Zhu, A1 - Andrew A. Chien, A1 - Chung-Kuan Cheng, PY - 2005 KW - null VL - 0 JA - 2012 IEEE 30th International Conference on Computer Design (ICCD) ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.84
Power consumption has become one of the ?rst order design considerations of the nano-scale VLSI designs. In this paper, we propose a methodology to synthesize energy-ef?cient Networks-on-Chip (NoCs). Our methodology features three key characters. First, we adopt a multicommodity ?ow formulation to unify network topologies, physical embedding, and wire style optimizations. Second, we utilize a variety of interconnect wire styles to achieve high performance low power on-chip communication. Third, we heuristically explore a large design space of network topologies. Experiments on a homogeneous communication demand model demonstrate that for a 4?4 NoC with torus topology, our methodology can achieve a power saving up to 35%.
Citation:
Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng, "Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz," iccd, pp.111-118, 2005 International Conference on Computer Design, 2005
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