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2005 International Conference on Computer Design
Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz
San Jose, California
October 02-October 05
ISBN: 0-7695-2451-6
Yuanfang Hu, Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA
Hongyu Chen, Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA
Yi Zhu, Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA
Andrew A. Chien, Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA
Chung-Kuan Cheng, Department of Compuqter Science and Engineering, University of California, San Diego, 9500 Gilman Dr., La Jolla, CA

Power consumption has become one of the ?rst order design considerations of the nano-scale VLSI designs. In this paper, we propose a methodology to synthesize energy-ef?cient Networks-on-Chip (NoCs). Our methodology features three key characters. First, we adopt a multicommodity ?ow formulation to unify network topologies, physical embedding, and wire style optimizations. Second, we utilize a variety of interconnect wire styles to achieve high performance low power on-chip communication. Third, we heuristically explore a large design space of network topologies. Experiments on a homogeneous communication demand model demonstrate that for a 4?4 NoC with torus topology, our methodology can achieve a power saving up to 35%.

Citation:
Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng, "Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz," iccd, pp.111-118, 2005 International Conference on Computer Design, 2005
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