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2012 IEEE 30th International Conference on Computer Design (ICCD) (2004)
San Jose, CA
Oct. 11, 2004 to Oct. 13, 2004
ISBN: 0-7695-2231-9
TABLE OF CONTENTS
pp. xii-xiii
pp. xv-xvi
pp. xvii-xviii
Keynote Addresses
Session 1.1 High-Speed and Energy-Efficient Circuit Design
Mohammad J. Akhbarizadeh , The University of Texas at Dallas
Mehrdad Nourani , The University of Texas at Dallas
Deepak S. Vijayasarathi , The University of Texas at Dallas
Poras T. Balsara , The University of Texas at Dallas
pp. 6-11
Srinivasa R. Sridhara , University of Illinois at Urbana Champaign
Arshad Ahmed , University of Illinois at Urbana Champaign
Naresh R. Shanbhag , University of Illinois at Urbana Champaign
pp. 12-17
Justin Hensley , University of North Carolina, Chapel Hill
Anselmo Lastra , University of North Carolina, Chapel Hill
Montek Singh , University of North Carolina, Chapel Hill
pp. 18-25
Robert D. Kenney , University of Wisconsin - Madison
Michael J. Schulte , University of Wisconsin - Madison
Mark A. Erle , International Business Machines, Poughkeepsie, NY
pp. 26-29
Magnus Sj?lander , Chalmers University of Technology, Sweden
Henrik Eriksson , Chalmers University of Technology, Sweden
Per Larsson-Edefors , Chalmers University of Technology, Sweden
pp. 30-33
Session 1.2 Energy-Efficient Processor Microarchitecture (1)
Aneesh Aggarwal , Binghamton University, NY
Manoj Franklin , University of Maryland, College Park
Oguz Ergin , Binghamton University, NY
pp. 36-41
Jung-Wook Park , CS, Yonsei University, Korea
Gi-Ho Park , Samsung Electronics Co., LTD. Giheung, Korea
Sung-Bae Park , Samsung Electronics Co., LTD. Giheung, Korea
Shin-Dug Kim , CS, Yonsei University, Korea
pp. 42-47
Pedro Chaparro , Intel Barcelona Research Center - Intel Labs - UPC
Jos? Gonz?lez , Intel Barcelona Research Center - Intel Labs - UPC
Antonio Gonz?lez , Intel Barcelona Research Center - Intel Labs - UPC
pp. 48-53
Yu Bai , Brown University, Providence, RI
R. Iris Bahar , Brown University, Providence, RI
pp. 54-57
Session 1.3 Scan Design and Test
S. Bhunia , Purdue University, West Lafayette, IN
H. Mahmoodi , Purdue University, West Lafayette, IN
S. Mukhopadhyay , Purdue University, West Lafayette, IN
D. Ghosh , Purdue University, West Lafayette, IN
K. Roy , Purdue University, West Lafayette, IN
pp. 60-65
Masayuki Tsukisaka , The University of Tokyo, Japan
Masashi Imai , The University of Tokyo, Japan
Takashi Nanya , The University of Tokyo, Japan
pp. 66-71
Sule Ozev , Duke University, Durham, NC
Alex Orailoglu , UCSD, San Diego, CA
pp. 72-77
Ho Fai Ko , McMaster University, Hamilton, ON, Canada
Nicola Nicolici , McMaster University, Hamilton, ON, Canada
pp. 78-81
Irith Pomeranz , Purdue University, W. Lafayette, IN
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 82-84
Session 2.1 Routing and Floorplanning
Hasan Arslan , University of Illinois-Chicago
Shantanu Dutt , University of Illinois-Chicago
pp. 86-92
Muhammet Mustafa Ozdal , Univ. of Illinois at Urbana-Champaign
Martin D. F. Wong , Univ. of Illinois at Urbana-Champaign
pp. 99-105
Andrew B. Kahng , University of CA, San Diego
Sherief Reda , University of CA, San Diego
pp. 106-110
Session 2.2 Formal Verification Embedded Tutorial
Chao Wang , University of Colorado at Boulder
Gary D. Hachtel , University of Colorado at Boulder
Fabio Somenzi , University of Colorado at Boulder
pp. 112-118
Session 2.3 Signal Integrity and Leakage
Srivathsan Krishnamohan , Michigan State University, East Lansing, MI
Nihar R. Mahapatra , Michigan State University, East Lansing, MI
pp. 126-131
Jihong Ren , University of British Columbia
Mark R. Greenstreet , University of British Columbia
pp. 132-137
Saumil Shah , University of Michigan, Ann Arbor
Kanak Agarwal , University of Michigan, Ann Arbor
Dennis Sylvester , University of Michigan, Ann Arbor
pp. 138-143
John Lach , University of Virginia
Jason Brandon , University of Virginia
Kevin Skadron , University of Virginia
pp. 144-150
Session 3.1 Special Session on High-Performance On-Chip Communication
Davide Pandini , STMicroelectronics, Italy
Cristiano Forzan , STMicroelectronics, Italy
Livio Baldi , STMicroelectronics, Italy
pp. 152-159
Mario R. Casu , Politecnico di Torino, Italy
Luca Macchiarulo , Politecnico di Torino, Italy
pp. 160-167
Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
Larry Pileggi , Carnegie Mellon University, Pittsburgh, PA
pp. 168-173
Gerard Mas , STMicroelectronics, France
Philippe Martin , Arteris, France
pp. 174-177
Session 3.2 Test Generation and Characterization
Jinkyu Lee , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 180-185
Jui-Jer Huang , Industrial Technology Research Institute, Taiwan
Jiun-Lang Huang , National Taiwan University, Taipei
pp. 186-191
Zhiyuan Wang , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
Kun-Han Tsai , Mentor Graphics Corporation, Wilsonville, OR
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR
pp. 192-199
Baris Arslan , University of California, San Diego
Ozgur Sinanoglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 200-203
Roy Emek , Haifa University Campus, Israel
Itai Jaeger , Haifa University Campus, Israel
Yoav Katz , Haifa University Campus, Israel
Yehuda Naveh , Haifa University Campus, Israel
pp. 204-206
Session 3.3 Physically-Aware Design Tools
Yinghua Li , UC Berkeley, Berkeley, CA
Rajeev Murgai , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Takashi Miyoshi , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Ashwini Verma , Amdocs, San Jose, CA
pp. 208-215
Ruiming Chen , Northwestern University, Evanston, IL
Hai Zhou , Northwestern University, Evanston, IL
pp. 216-221
Anup Kumar Sultania , University of Minnesota, Minneapolis, MN
Dennis Sylvester , University of Michigan, Ann Arbor, MI
Sachin S. Sapatnekar , University of Minnesota, Minneapolis, MN
pp. 228-233
Session 4.1 Energy-Efficient Processor Microarchitecture (2)
Ed Grochowski , Intel Labs, Santa Clara, CA
Ronny Ronen , Intel Israel
John Shen , Intel Labs, Santa Clara, CA
Hong Wang , Intel Labs, Santa Clara, CA
pp. 236-243
Nikil Mehta , Brown University, Providence, RI
Brian Singer , Brown University, Providence, RI
R. Iris Bahar , Brown University, Providence, RI
Michael Leuchtenburg , Hampshire College, Amherst, MA
Richard Weiss , Hampshire College, Amherst, MA
pp. 244-249
Grigorios Magklis , Intel Barcelona Research Center
Jos? Gonz?lez , Intel Barcelona Research Center
Antonio Gonz?lez , Intel Barcelona Research Center
pp. 250-255
Session 4.2 Power and Timing Optimization
Feng Gao , University of Michigan, Ann Arbor
John P. Hayes , University of Michigan, Ann Arbor
pp. 258-264
Kai Wang , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 265-271
Murari Mani , University of Texas at Austin
Michael Orshansky , University of Texas at Austin
pp. 272-277
Session 4.3 Novel Processor Design
Mark Franklin , Washington University in St. Louis
Roger Chamberlain , Washington University in St. Louis; Data Search Systems, Inc., St. Louis, MO
Michael Henrichs , Data Search Systems, Inc., St. Louis, MO
Berkley Shands , Washington University in St. Louis
Jason White , Data Search Systems, Inc., St. Louis, MO
pp. 280-287
Roland E. Wunderlich , Computer Architecture Laboratory at Carnegie Mellon
James C. Hoe , Computer Architecture Laboratory at Carnegie Mellon
pp. 288-294
Chun-Ho Kim , KAIST (Korea Advanced Institute of Science and Technology)
Lee-Sup Kim , KAIST (Korea Advanced Institute of Science and Technology)
pp. 295-300
Session 5.1 Emerging Technologies Special Session
Michael T. Niemier , Georgia Institute of Technology
Ramprasad Ravichandran , Georgia Institute of Technology
Peter M. Kogge , University of Notre Dame
pp. 302-309
Ahmed Usman Khalid , McGill University, Montreal, Quebec
Zeljko Zilic , McGill University, Montreal, Quebec
Katarzyna Radecka , Concordia University, Montreal, Quebec
pp. 310-315
Bryan Black , Intel Corporation
Donald W. Nelson , Intel Corporation
Clair Webb , Intel Corporation
Nick Samra , Intel Corporation
pp. 316-318
Session 5.2 Cache Memory Design
Annie Y. Zeng , Rensselaer Polytechnic Institute, Troy, NY
Ken Rose , Rensselaer Polytechnic Institute, Troy, NY
Ronald J. Gutmann , Rensselaer Polytechnic Institute, Troy, NY
pp. 320-325
Joshua L. Kihm , University of Colorado at Boulder
Daniel A. Connors , University of Colorado at Boulder
pp. 326-331
Alex Veidenbaum , University of California, Irvine
Dan Nicolaescu , University of California, Irvine
pp. 332-335
Session 6.1 Layout-Driven Circuit Optimization
Yajun Ran , University of California, Santa Barbara
Malgorzata Marek-Sadowska , University of California, Santa Barbara
pp. 338-343
Yi Zou , Tsinghua University, Beijing, P.R. China
Yici Cai , Tsinghua University, Beijing, P.R. China
Qiang Zhou , Tsinghua University, Beijing, P.R. China
Xianlong Hong , Tsinghua University, Beijing, P.R. China
Sheldon X.-D. Tan , University of California at Riverside, USA
pp. 344-349
Ingmar Neumann , University of Kaiserslautern, Germany
Dominik Stoffel , University of Kaiserslautern, Germany
Kolja Sulimma , University of Kaiserslautern, Germany
Michel Berkelaar , Magma Design Automation Inc., Cupertino, CA, USA
Wolfgang Kunz , University of Kaiserslautern, Germany
pp. 350-353
Dongku Kang , Purdue University, West Lafayette, IN
Hunsoo Choo , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 354-357
Session 6.2 Instruction-Level Parallelism (1)
Srikanth T. Srinivasan , Intel Corporation
Haitham Akkary , Intel Corporation
Tom Holman , Intel Corporation
Konrad Lai , Intel Corporation
pp. 360-367
Rama Sangireddy , University of Texas at Dallas
Arun K. Somani , Iowa State University, Ames
pp. 368-374
Yau Chin , Harvard University
John Sheu , Harvard University
David Brooks , Harvard University
pp. 375-378
Session 6.3 Power Estimation and Minimization
Siddharth Garg , Indian Institute of Technology-Madras
Siddharth Tata , Indian Institute of Technology-Madras
Ravishankar Arunachalam , Indian Institute of Technology-Madras
pp. 380-386
Donald Chai , University of California at Berkeley, CA, USA
Andreas Kuehlmann , University of California at Berkeley, CA, USA; Cadence Berkeley Labs, Berkeley, CA, USA
pp. 387-392
Mirko Loghi , Universit? di Verona, Italy
Luca Benini , Universit? di Bologna, Italy
Massimo Poncino , Universit? di Verona, Italy
pp. 393-396
Zhaohui Huang , Michigan State University, East Lansing, MI
Peixin Zhong , Michigan State University, East Lansing, MI
pp. 397-400
Session 7.1 Formal Verification Techniques
Nikhil Kikkeri , Southern Methodist University, Dallas, TX
Peter-Michael Seidel , Southern Methodist University, Dallas, TX
pp. 402-408
Kelvin Ng , University of British Columbia
Alan J. Hu , University of British Columbia
Jin Yang , Intel Corporation
pp. 409-416
Chen-Ling Chou , National Chiao Tung University, Taiwan
Chun-Yao Wang , National Tsing Hua University, Taiwan
Geeng-Wei Lee , National Chiao Tung University, Taiwan
Jing-Yang Jou , National Chiao Tung University, Taiwan
pp. 417-419
Session 7.2 Networks on Chips
Krishnan Srinivasan , Arizona State University, Tempe
Karam S. Chatha , Arizona State University, Tempe
Goran Konjevod , Arizona State University, Tempe
pp. 422-429
W. Hung , The Pennsylvania State University
C. Addo-Quaye , The Pennsylvania State University
T. Theocharides , The Pennsylvania State University
Y. Xie , The Pennsylvania State University
N. Vijaykrishnan , The Pennsylvania State University
M. J. Irwin , The Pennsylvania State University
pp. 430-437
Chae-Eun Rhee , Samsung Electronics Co., Ltd, Suwon, Korea
Han-You Jeong , Seoul National University, Korea
Soonhoi Ha , Seoul National University, Korea
pp. 438-443
Session 7.3 Novel Processor Architecture
Liang Han , Chinese Academy of Science
Jie Chen , Chinese Academy of Science
Chaoxian Zhou , Chinese Academy of Science
Ying Li , Chinese Academy of Science
Xin Zhang , Chinese Academy of Science
Zhibi Liu , Chinese Academy of Science
Xiaoyun Wei , Chinese Academy of Science
Baofeng Li , Chinese Academy of Science
pp. 446-451
A. Murat Fiskiran , Princeton University
Ruby B. Lee , Princeton University
pp. 452-457
Jiangjiang Liu , University at Buffalo, SUNY, NY
Krishnan Sundaresan , Michigan State University, East Lansing
Nihar R. Mahapatra , Michigan State University, East Lansing
pp. 458-463
Session 8.1 Instruction-Level Parallelism (2)
Feng Shi , Yale University, New Haven, CT
Sobeeh Almukhaizim , Yale University, New Haven, CT
Pey-Chang Lin , Yale University, New Haven, CT
Yiorgos Makris , Yale University, New Haven, CT
pp. 466-471
Sriram Nadathur , Iowa State University, Ames, Iowa
Akhilesh Tyagi , Iowa State University, Ames, Iowa
pp. 472-479
Oguz Ergin , State University of New York, Binghamton, NY
Deniz Balkan , State University of New York, Binghamton, NY
Dmitry Ponomarev , State University of New York, Binghamton, NY
Kanad Ghose , State University of New York, Binghamton, NY
pp. 480-487
Session 8.2 Topics in Synthesis and Co-Simulation
Hu Huang , University of Maryland, College Park, MD
Joseph B. Bernstein , University of Maryland, College Park, MD
Martin Peckerar , University of Maryland, College Park, MD
Ji Luo , University of Maryland, College Park, MD
pp. 490-495
F. Fummi , Universit? di Verona, Italy
S. Martini , Embedded Systems Design Center, Verona, Italy
M. Monguzzi , Sitek S.p.A., S.G. Lupatoto, Italy
G. Perbellini , Embedded Systems Design Center, Verona, Italy
M. Poncino , Universit? di Verona, Italy
pp. 496-501
Jinwen Xi , Michigan State University, East Lansing, MI
Peixin Zhong , Michigan State University, East Lansing, MI
pp. 502-504
J. Cortadella , Univ. Polit?cnica Catalunya, Barcelona, Spain
A. Kondratyev , Cadence Berkeley Labs, Berkeley, CA
L. Lavagno , Politenico di Torino, Italy
C. Sotiriou , ICS-FORTH, Crete, Greece
pp. 505-508
Session 8.3 Low-Power Architecture
Vassos Soteriou , Princeton University, Princeton, NJ
Li-Shiuan Peh , Princeton University, Princeton, NJ
pp. 510-517
Yao Guo , University of Massachusetts, Amherst, MA
Saurabh Chheda , BlueRISC Inc., Hadley, MA
Israel Koren , University of Massachusetts, Amherst, MA
C. Mani Krishna , University of Massachusetts, Amherst, MA
Csaba Andras Moritz , University of Massachusetts, Amherst, MA
pp. 518-523
Hee-Kwan Son , Samsung Electronics Co., Korea
Sang-Geun Oh , Samsung Electronics Co., Korea
pp. 524-531
Session 9.1 Test Generation
Scott Ollivierre , McMaster University, ON, Canada
Adam B. Kinsman , McMaster University, ON, Canada
Nicola Nicolici , McMaster University, ON, Canada
pp. 534-539
Pallav Gupta , Princeton University, NJ
Rui Zhang , Princeton University, NJ
Niraj K. Jha , Princeton University, NJ
pp. 540-543
Hung-Yau Lin , National Taiwan University, Taipei
Hong-Zu v , National Taiwan University, Taipei
Fu-Min Yeh , Chung-Shan Institute of Science and Technology, Taoyuan, Taiwan
Ing-Yi Chen , National Taipei University of Technology, Taiwan
Sy-Yen Kuo , National Taiwan University, Taipei
pp. 544-546
Session 9.2 Network Routing
H. H. Najaf-abadi , IPM, Tehran, Iran
H. Sarbazi-azad , IPM, Tehran, Iran; Sharif Univ. of Technology, Tehran, Iran
pp. 548-553
Raymond W. Baldwin , University of Illinois at Chicago
Enrico Ng , University of Illinois at Chicago
pp. 554-559
Session 9.3 Placement and Floorplanning
Hung-Ming Chen , National Chiao Tung University, Hsinchu, Taiwan
I-Min Liu , Cadence Design Systems Inc., San Jose, CA
Martin D.F. Wong , University of Illinois at Urbana-Champaign, Urbana, IL
Muzhou Shao , Synopsys Inc., Mountain View, CA
Li-Da Huang , Texas Instruments, Austin, TX
pp. 562-567
Meng-Chen Wu , National Chiao Tung University, Taiwan
Yao-Wen Chang , National Taiwan University, Taipei
pp. 568-571
Hai Zhou , Northwestern University, Evanston, IL
Jia Wang , Northwestern University, Evanston, IL
pp. 572-575
Author Index (PDF)
pp. 576-578
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