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2003 IEEE International Conference on Computer Design (ICCD'03)
San Jose, California
October 13-October 15
ISBN: 0-7695-2025-1
Table of Contents
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Welcome (PDF)
pp. xiii
Keynotes
Session 1.1 Energy Efficiency
Jaume Abella, Universitat Polit?cnica de Catalunya, Barcelona (Spain)
Antonio Gonz?lez, Universitat Polit?cnica de Catalunya, Barcelona (Spain)
pp. 8
Jaume Abella, Universitat Polit?cnica de Catalunya, Barcelona (Spain)
Antonio Gonz?lez, Universitat Polit?cnica de Catalunya, Barcelona (Spain)
pp. 14
Session 1.2 Timing Verification
Hao Zheng, IBM Microelectronics in Burlington, VT
Chris J. Myers, University of Utah, Salt Lake City
David Walter, University of Utah, Salt Lake City
Scott Little, University of Utah, Salt Lake City
Tomohiro Yoneda, National Institute of Informatics in Tokyo, Japan.
pp. 28
Edmund M. Clarke, Carnegie Mellon University
Daniel Kroening, Carnegie Mellon University
Karen Yorav, Carnegie Mellon University
pp. 48
Session 1.3 Electrical Analysis for System LSI
Session 2.1 Power Optimization
Payman Zarkesh-Ha, LSI Logic Corporation
Ken Doniger, LSI Logic Corporation
William Loh, LSI Logic Corporation
Dechang Sun, Advance Custom Memory Group, AMINN
Rick Stephani, Advance Custom Memory Group, AMINN
Gordon Priebe, Advance Custom Memory Group, AMINN
pp. 84
Afshin Abdollahi, University of Southern California
Massoud Pedarm, University of Southern California
Farzan Fallah, Fujitsu Labs of America
Indradeep Ghosh, Fujitsu Labs of America
pp. 90
Hiroaki Suzuki, Purdue University, West Lafayette
Woopyo Jeong, Purdue University, West Lafayette
Kaushik Roy, Purdue University, West Lafayette
pp. 103
Session 2.2 Invited Session: Gene Chip Design
Embedded Tutorial
Andrew B. Kahng, University of California at San Diego
Ion I. Mandoiu, University of Connecticut
Sherief Reda, University of California at San Diego
Xu Xu, University of California at San Diego
Alex Z. Zelikovsky, Georgia State University
pp. 116
Session 2.3 System Level Design
Nattawut Thepayasuwan, State University of New York at Stony Brook
Vaishali Damle, State University of New York at Stony Brook
Alex Doboli, State University of New York at Stony Brook
pp. 126
Vikas Chandra, Carnegie Mellon University, Pittsburgh, PA
Gary Carpenter, IBM Austin Research Lab
Jeff Burns, IBM Austin Research Lab
pp. 134
Manev Luthra, University of California at Irvine
Sumit Gupta, University of California at Irvine
Nikil Dutt, University of California at Irvine
Rajesh Gupta, University of California at San Diego
Alex Nicolau, University of California at Irvine
pp. 140
Alessandro Pinto, University of California at Berkeley
Luca P. Carloni, University of California at Berkeley
Alberto L. Sangiovanni-Vincentelli, University of California at Berkeley
pp. 146
Mehrdad Reshadi, University of California, Irvine
Nikil Dutt, University of California, Irvine
pp. 151
Session 3.1 Systems Performance
Karthikeyan Sankaralingam, The University of Texas at Austin
Vincent Ajay Singh, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
Doug Burger, The University of Texas at Austin
pp. 170
Session 3.2 Micro Processor Test & Diagnosis
Joel Grodstein, Intel Corporation, Shrewsbury, MA
Dilip Bhavsar, Intel Corporation, Shrewsbury, MA
Vijay Bettada, Intel Corporation, Shrewsbury, MA
Richard Davies, Intel Corporation, Shrewsbury, MA
pp. 180
Zhiyuan Wang, University of California, Santa Barbara
Malgorzata Marek-Sadowska, University of California, Santa Barbara
Kun-Han Tsai, Mentor Graphics Corporation, Wilsonville, OR
Janusz Rajski, Mentor Graphics Corporation, Wilsonville, OR
pp. 198
Session 3.3 Physical Design
Noriyuki Ito, Fujitsu Limited, Japan
Hiroaki Komatsu, Fujitsu Limited, Japan
Yoshiyasu Tanamura, Fujitsu Limited, Japan
Ryoichi Yamashita, Fujitsu Limited, Japan
Hiroyuki Sugiyama, Fujitsu Limited, Japan
Yaroku Sugiyama, Fujitsu Limited, Japan
Hirofumi Hamamura, Fujitsu Limited, Japan
pp. 204
Yangdong (Steven) Deng, Carnegie Mellon University, Pittsburgh, PA
Wojciech Maly, Carnegie Mellon University, Pittsburgh, PA
pp. 211
Bo-Kyung Choi, University of California, Los Angeles
Huaiyu Xu, University of California, Los Angeles
Maogang Wang, Cadence Design Systems, San Jose, CA
Majid Sarrafzadeh, University of California, Los Angeles
pp. 218
Session 4.1 Performance Optimization
Session 4.2 Clock & Signal Distribution
Steven C. Chan, Columbia University, New York, NY
Kenneth L. Shepard, Columbia University, New York, NY
Phillip J. Restle, IBM T.J Watson Research Center, NY
pp. 248
Ganesh Balamurugan, University of Illinois at Urbana-Champaign, Urbana, IL
Naresh Shanbhag, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 254
Daniel Eckerbert, Chalmers University of Technology, Sweden
Lars "J." Svensson, Chalmers University of Technology, Sweden
Per Larsson-Edefors, Chalmers University of Technology, Sweden
pp. 261
Shidhartha Das, University of Michigan, Ann Arbor
Kanak Agarwal, University of Michigan, Ann Arbor
David Blaauw, University of Michigan, Ann Arbor
Dennis Sylvester, University of Michigan, Ann Arbor
pp. 264
Session 4.3 Performance and Power-Driven Physical Design
Nataraj Akkiraju, Intel Corporation, Santa Clara, CA
Mosur Mohan, Intel Corporation, Hilsboro, OR
pp. 270
Rishi Chaturvedi, Texas A&M University, College Station
Jiang Hu, Texas A&M University, College Station
pp. 282
Session 5.1 Instruction Execution
Shih-Chang Lai, SiS Corporation, Hsinchu, Taiwan
Shih-Lien Lu, Intel corp., Hillsboro, OR
pp. 290
Tay-Jyi Lin, National Chiao Tung University
Chin-Chi Chang, National Chiao Tung University
Chen-Chia Lee, National Chiao Tung University
Chein-Wei Jen, National Chiao Tung University
pp. 307
Mohamed Zahran, University of Maryland, College Park
Manoj Franklin, University of Maryland, College Park
pp. 313
Session 5.2 Invited Session: Test Compression Technology
Subhasish Mitra, Intel Corporation, Sacramento, CA
Kee Sup Kim, Intel Corporation, Sacramento, CA
pp. 326
Session 5.3 Physical Design for Regular Fabrics and FPGA's
Aiqun Cao, School of Electrical and Purdue University
Cheng-Kok Koh, School of Electrical and Purdue University
pp. 338
Session 6.1 Array Design Optimization
V. Delaluz, The Pennsylvania State University
M. Kandemir, The Pennsylvania State University
A. Sivasubramaniam, The Pennsylvania State University
M. J. Irwin, The Pennsylvania State University
N. Vijaykrishnan, The Pennsylvania State University
pp. 358
Gurhan Kucuk, State University of New York, Binghamton
Oguz Ergin, State University of New York, Binghamton
Dmitry Ponomarev, State University of New York, Binghamton
Kanad Ghose, State University of New York, Binghamton
pp. 364
Peter Petrov, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 371
Jos? Gonz?lez, Universitat Polit?cnica de Catalunya
Antonio Gonz?lez, Universitat Polit?cnica de Catalunya
pp. 375
Session 6.2 Test Compaction
Session 6.3 Invited Session: Techniques for Synthesizing into Fabrics
C. Ross Ogilvie, IBM Corporation
Richard Ray, IBM Corporation
Robert Devins, IBM Corporation
Mark Kautzman, IBM Corporation
Michael Hale, IBM Corporation
Reinaldo Bergamaschi, IBM Corporation
Bob Lynch, IBM Corporation
Santosh Gaur, IBM Corporation
pp. 402
Session 7.1 Hardware Partitioning
Session 7.2 Energy-Aware Design and Application
Saraju P. Mohanty, University of South Florida, Tampa
N. Ranganathan, University of South Florida, Tampa
Sunil K. Chappidi, University of South Florida, Tampa
pp. 441
Farhad Ghasemi-Tari, Univ. of Southern California, Los Angeles
Peng Rong, Univ. of Southern California, Los Angeles
Massoud Pedram, Univ. of Southern California, Los Angeles
pp. 444
Session 7.3 Invited Session: High-Speed Design Issues and Test Challenges
M.-J. Edward Lee, Velio Communications, Inc.
William J. Dally, Stanford University; Velio Communications, Inc.
Ramin Farjad-Rad, Velio Communications, Inc.
Hiok-Tiaq Ng, Velio Communications, Inc.
Ramesh Senthinathan, Velio Communications, Inc.
John Edmondson, Velio Communications, Inc.
John Poulton, Velio Communications, Inc.
pp. 454
Session 8.1 Efficiency and Reliability
Chanik Park, SAMSUNG Electronics, Co., Ltd.
Jaeyu Seo, SAMSUNG Electronics, Co., Ltd.
Dongyoung Seo, SAMSUNG Electronics, Co., Ltd.
Shinhan Kim, SAMSUNG Electronics, Co., Ltd.
Bumsoo Kim, SAMSUNG Electronics, Co., Ltd.
pp. 474
Premkishore Shivakumar, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
Charles R. Moore, The University of Texas at Austin
Doug Burger, The University of Texas at Austin
pp. 481
Zhijian Lu, University of Virginia, Charlottesville
John Lach, University of Virginia, Charlottesville
Mircea Stan, University of Virginia, Charlottesville
Kevin Skadron, University of Virginia, Charlottesville
pp. 489
Session 8.2 Novel Methods in Logic Synthesis
Guoqiang Wang, University of California at Berkeley, CA
Andreas Kuehlmann, University of California at Berkeley, CA; Cadence Berkeley Labs, Berkeley, CA
Alberto Sangiovanni-Vincentelli, University of California at Berkeley, CA
pp. 498
Elena Dubrova, Royal Institute of Technology, IMIT/KTH, Stockholm, Sweden
Maxim Teslenko, Royal Institute of Technology, IMIT/KTH, Stockholm, Sweden
Johan Karlsson, Royal Institute of Technology, IMIT/KTH, Stockholm, Sweden
pp. 504
Samir Sapra, Carnegie Mellon University, Pittsburgh, PA
Michael Theobald, Carnegie Mellon University, Pittsburgh, PA
Edmund Clarke, Carnegie Mellon University, Pittsburgh, PA
pp. 510
Session 9.1 Communications and Context Management
Santithorn Bunchua, Georgia Institute of Technology, Atlanta
D. Scott Wills, Georgia Institute of Technology, Atlanta
Linda M. Wills, Georgia Institute of Technology, Atlanta
pp. 532
Matteo Dall'Osso, University of Bologna, DEIS
Gianluca Biccari, University of Bologna, DEIS
Luca Giovannini, University of Bologna, DEIS
Davide Bertozzi, University of Bologna, DEIS
Luca Benini, University of Bologna, DEIS
pp. 536
Session 9.2 Board Test and Power-Aware Test
Ozgur Sinanoglu, University of California, San Diego
Alex Orailoglu, University of California, San Diego
pp. 542
Mehrdad Nourani, The University of Texas at Dallas
James Chin, The University of Texas at Dallas
pp. 548
M. H. Tehranipour, The University of Texas at Dallas, Richardson
N. Ahmed, The University of Texas at Dallas, Richardson
M. Nourani, The University of Texas at Dallas, Richardson
pp. 554
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