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2002 IEEE International Conference on Computer Design (ICCD'02)
Freiburg, Germany
September 16-September 18
ISBN: 0-7695-1700-5
Table of Contents
Introduction
Keynote Addresses
Session 1.1: Special Invited Session: Computers in Media, Mobile and Servers
Atsushi Mizuno, Toshiba Corporation
Kazuyoshi Kohno, Toshiba Corporation
Ryuichiro Ohyama, Toshiba Corporation
Takahiro Tokuyoshi, Toshiba Corporation
Hironori Uetani, Toshiba Corporation
Hans Eichel, Toshiba Electronics Europe GmbH
Takashi Miyamori, Toshiba Corporation
Nobu Matsumoto, Toshiba Corporation
Masataka Matsui, Toshiba Corporation
pp. 2
Session 1.2: Physical Design
Hongyu Chen, University of California at Dan Diego
Bo Yao, University of California at Dan Diego
Feng Zhou, University of California at Dan Diego
Chung-Kuan Cheng, University of California at Dan Diego
pp. 30
Xiaojian Yang, University of California at Los Angeles
Bo-Kyung Choi, University of California at Los Angeles
Majid Sarrafzadeh, University of California at Los Angeles
pp. 45
Session 1.3: Verification
Partha S. Roop, University of Auckland
A. Sowmya, University of New South Wales
S. Ramesh, Indian Institute of Technology at Bombay
pp. 50
Session 2.1: Special Invited Session: Design ITRS 2001 — Issues and Solutions
Kurt Keutzer, University of California at Berkeley
Sharad Malik, Princeton University
A. Richard Newton, University of California at Berkeley
pp. 84
Session 2.2: Data Path Elements for Multi-GHz Design
Oguz Ergin, State University of New York at Binghamton
Kanad Ghose, State University of New York at Binghamton
Gurhan Kucuk, State University of New York at Binghamton
Dmitry Ponomarev, State University of New York at Binghamton
pp. 118
Session 2.3: Multimedia and Arithmetic
Jari Nikara, Tampere University of Technology
Stamatis Vassiliadis, Technical University of Delft
Jarmo Takala, Tampere University of Technology
Mihai Sima, Technical University of Delft
Petri Liuha, Nokia Research Center
pp. 126
J.-A. Piñeiro, Universidad Santiago de Compostela
M. D. Ercegovac, University of California at Los Angeles
J. D. Bruguera, Universidad Santiago de Compostela
pp. 132
Tomas Lang, University of California at Irvine
Javier D. Bruguera, University of Santiago de Compostela
pp. 145
Session 3.1: Methodology Issues for High Performance Designs
Rita Yu Chen, Sun Microsystems, Inc.
Paul Yip, Sun Microsystems, Inc.
Georgios Konstadinidis, Sun Microsystems, Inc.
Andrew Demas, Sun Microsystems, Inc.
Fabian Klass, Sun Microsystems, Inc.
Rob Mains, Sun Microsystems, Inc.
Margaret Schmitt, Sun Microsystems, Inc.
Dina Bistry, Sun Microsystems, Inc.
pp. 158
B. Chappell, Intel Corporation
X. Wang, Intel Corporation
P. Patra, Intel Corporation
P. Saxena, Intel Corporation
J. Vendrell, Intel Corporation
S. Gupta, Intel Corporation
S. Varadarajan, Intel Corporation
W. Gomes, Intel Corporation
S. Hussain, Intel Corporation
H. Krishnamurthy, Intel Corporation
M. Venkateshmurthy, Intel Corporation
S. Jain, Intel Corporation
pp. 164
Session 3.2: Low-Power Microarchitecture
Hongbo Yang, University of Delaware
R. Govindarajan, Indian Institute of Science at Bangalore
Guang R. Gao, University of Delaware
Kevin B. Theobald, University of Delaware
pp. 174
Esther Y. Cheng, University of California at San Diego
Feng Zhou, University of California at San Diego
Bo Yao, University of California at San Diego
Chung-Kuan Cheng, University of California at San Diego
Ronald Graham, University of California at San Diego
pp. 180
Session 3.3: Design for Testability
Kohei Miyase, Kyusyu Institute of Technology
Seiji Kajihara, Kyusyu Institute of Technology
Irith Pomeranz, Purdue University
Sudhakar M. Reddy, University of Iowa
pp. 194
Michiko Inoue, Nara Institute of Science and Technology
Chikateru Jinno, Nara Institute of Science and Technology
Hideo Fujiwara, Nara Institute of Science and Technology
pp. 200
C. Galke, Brandenburg University of Technology Cottbus
M. Pflanz, IBM Deutschland Entwicklung GmbH
H. T. Vierhaus, Brandenburg University of Technology Cottbus
pp. 210
Session 4.1: Special Invited Session: Sensor Networks: New Architecture and Synthesis Challenges
Lewis Girod, University of Califnornia at Los Angeles
Vladimir Bychkovskiy, University of Califnornia at Los Angeles
Jeremy Elson, University of Califnornia at Los Angeles
Deborah Estrin, University of Califnornia at Los Angeles
pp. 214
Andreas Savvides, University of California at Los Angeles
Mani B. Srivastava, University of California at Los Angeles
pp. 220
Jessica Feng, University of California at Los Angeles
Farinaz Koushanfar, University of California at Berkeley
Miodrag Potkonjak, University of California at Los Angeles
pp. 226
Session 4.2: Computer Systems Design and Applications I
Witawas Srisa-an, University of Nebraska at Lincoln
Chia-Tien Dan Lo, University of Texas at San Antonio
J. Morris Chang, Iowa State University
pp. 249
Session 4.3: Analog Test and Dependability
Sule Ozev, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 258
I-De Huang, University of Southern California
Sandeep K. Gupta, University of Southern California
Melvin A. Breuer, University of Southern California
pp. 265
Jacob Savir, New Jersey Institute Of Technology
Zhen Guo, New Jersey Institute Of Technology
pp. 273
Session 5.1: Special Session: The Imagine Processor
Ujval J. Kapasi, Stanford University
William J. Dally, Stanford University
Scott Rixner, Rice University
John D. Owens, Stanford University
Brucek Khailany, Stanford University
pp. 282
Brucek Khailany, Stanford University
William J. Dally, Stanford University
Andrew Chang, Stanford University
Ujval J. Kapasi, Stanford University
Jinyung Namkoong, Stanford University
Brian Towles, Stanford University
pp. 289
John D. Owens, Stanford University
Scott Rixner, Rice University
Ujval J. Kapasi, Stanford University
Peter Mattson, Stanford University
Brian Towles, Stanford University
Ben Serebrin, Stanford University
William J. Dally, Stanford University
pp. 295
Ben Serebrin, Stanford University
John D. Owens, Stanford University
Chen H. Chen, University of Southern California
Stephen P. Crago, University of Southern California
Ujval J. Kapasi, Stanford University
Peter Mattson, Stanford University
Jinyung Namkoong, Stanford University
Scott Rixner, Rice University
William J. Dally, Stanford University
pp. 303
Session 5.2: Low Power Circuit Techniques
Shanq-Jang Ruan, National Taiwan University
Edwin Naroska, University of Dortmund
Chia-Lin Ho, National Taiwan University
Feipei Lai, National Taiwan University
pp. 327
Session 5.3: Cache Memories
Jinwoo Kim, Georgia Institute of Technology
Krishna V. Palem, Georgia Institute of Technology
Weng-Fai Wong, National University of Singapore
pp. 340
Afzal Hossain, Syracuse University
Daniel J. Pease, Syracuse University
James S. Burns, Syracuse University
Nasima Parveen, Syracuse University
pp. 348
Session 6.1: Special Invited Session: Processors in Automotive Systems
Paolo Giusto, Cadence Design Systems
Jean-Yves Brunel, Cadence Design Systems
Alberto Ferrari, Parades GEIE
Eliane Fourgeau, Cadence Design Systems
Luciano Lavagno, Cadence Design Systems
pp. 370
Paolo Giusto, Cadence Design Systems
Jean-Yves Brunel, Cadence Design Systems
Alberto Ferrari, Parades EEIG
Eliane Fourgeau, Cadence Design Systems
Luciano Lavagno, Cadence Design Systems
Barry Orourke, Cadence Design Systems
Emanuele Guasto, Parades EEIG
pp. 379
Session 6.2: Power Management and High Level Synthesis
D. Duarte, Intel Corporation
N. Vijaykrishnan, Pennsylvania State University
M.J. Irwin, Pennsylvania State University
H-S Kim, Pennsylvania State University
G. McFarland, Intel Corporation
pp. 382
Seda Ogrenci Memik, University of California at Los Angeles
Farzan Fallah, Fujitsu Laboratories of America, Inc.
pp. 395
Session 6.3: Speculative and Packet Oriented Architectures
Carlos Molina, Universitat Rovira i Virgili
Antonio González, Universitat Polit?cnica de Catalunya
Jordi Tubella, Universitat Polit?cnica de Catalunya
pp. 402
Manvi Agarwal, Indian Institute of Science at Bangalore
S. K. Nandy, Indian Institute of Science at Bangalore
J.v. Eijndhoven, Philips Research Laboratories
S. Balakrishnan, Philips Research Laboratories
pp. 408
Session 7.1: Interconnect Modeling and Analysis
Session 7.2: Issues in Processor Architecture
Zhigang Hu, Princeton University
Philo Juang, Princeton University
Kevin Skadron, University of Virginia
Douglas Clark, Princeton University
Margaret Martonosi, Princeton University
pp. 442
Ann Gordon-Ross, University of California at Riverside
Frank Vahid, University of California at Riverside and University of California at Irvine
pp. 446
Session 7.3: Low Power Test, Diagnosis
Baris Arslan, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 480
Session 8.1: System Design Issues
L. Benini, Università di Bologna
D. Bertozzi, Università di Bologna
D. Bruni, Università di Bologna
N. Drago, Università di Verona
F. Fummi, Università di Verona
M. Poncino, Università di Verona
pp. 494
Session 8.2: Computer Systems Design and Applications II
Author Index
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