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2001 IEEE International Conference on Computer Design (ICCD'01)
Austin, Texas
September 23-September 26
ISBN: 0-7695-1200-3
Table of Contents
Keynote Addresses
Session 1.1: Asynchronous Techniques
Session 1.2: Embedded Tutorial
Security of Smartcard Integrated Circuits
Session 1.3: Architectural Modeling: Performance and Power Analysis
H. S. Kim, The Pennsylvania State University
N. Vijaykrishnan, The Pennsylvania State University
M. Kandemir, The Pennsylvania State University
M. J. Irwin, The Pennsylvania State University
pp. 0040
Session 2.1: Caching
Aamer Jaleel, University of Maryland at College Park
Bruce Jacob, University of Maryland at College Park
pp. 0062
Weiyu Tang, University of California, Irvine
Rajesh Gupta, University of California, Irvine
Alexandru Nicolau, University of California, Irvine
pp. 0068
Session 2.2: Simulation Based Verification
Serdar Tasiran, Compaq Systems Research Center
Farzan Fallah, Fujitsu Labs of America, Inc.
David G. Chinnery, University of California, Berkeley
Scott J. Weber, University of California, Berkeley
Kurt Keutzer, University of California, Berkeley
pp. 0082
Session 2.3: Modeling of Capacitance and Crosstalk Noise
Saisanthosh Balakrishnan, University of Wisconsin-Madison
Jong Hyuk Park, University of Wisconsin-Madison
Hyungsuk Kim, University of Wisconsin-Madison
Yu-Min Lee, University of Wisconsin-Madison
Charlie C.-P. Chen, University of Wisconsin-Madison
pp. 0098
Session 3.1: Improving the Performance of Caching Structures
Jung-Hoon Lee, Yonsei University
Jang-Soo Lee, Yonsei University
Shin-Dug Kim, Yonsei University
Seh-Woong Jeong, Samsung Electronics Co., Ltd.
pp. 0118
Doug Burger, University of Texas at Austin
Thomas R. Puzak, IBM Corporation T. J. Watson Research Center
Wei-Fen Lin, University of Michigan
Steven K. Reinhardt, University of Michigan
pp. 0124
Edward S. Tam, Apple Computer, Inc.
Stevan A. Vlaovic, The University of Michigan
Gary S. Tyson, The University of Michigan
Edward S. Davidson, The University of Michigan
pp. 0133
Session 3.2: Test Pattern Generation, Test Compaction, and Test Point Insertion for Synchronous Sequential Circuits
Session 3.3: Invited Session: Power 4 Microprocessor- Organizer: J. M. Tendler
Power4 Integration
Session 4.1: Embedded Tutorial
Session 4.2: Computer Arithmetic
Pablo I. Balzola, Lehigh University
Michael J. Schulte, Lehigh University
Jie Ruan, Lehigh University
John Glossner, Sandbridge Technologies
Erdem Hokenek, Sandbridge Technologies
pp. 0172
Session 4.3: Circuit Sizing and Optimization
Session 5.1: Clocking and Time-Domain Measurements
Session 5.2: Processor Microarchitecture
Juan L. Aragón, Universidad de Murcia
José González, Universidad de Murcia
José M. García, Universidad de Murcia
Antonio González, Universitat Polit?cnica de Catalunya
pp. 0228
Yan Solihin, University of Illinois at Urbana-Champaign
Kirk W. Cameron, University of South Carolina
Yong Luo, Intel Corporation
Dominique Lavenier, IRISA/CNRS
Maya Gokhale, Los Alamos National Laboratory
pp. 0234
Session 5.3: Invited Session: Taming Tons of Gigabytes: Innovations in Disk Drive Electronics
Georg Pelz, Infineon Technologies, Memory Products, Network and Computer Storage
pp. 0256
James Jeppesen, Infineon Technologies; Memory Products, Network and Computer Storage
Walt Allen, Infineon Technologies; Memory Products, Network and Computer Storage
Steve Anderson, Infineon Technologies; Memory Products, Network and Computer Storage
Michael Pilsl, Infineon Technologies; Memory Products, Network and Computer Storage
pp. 0262
W. Sereinig, Infineon Technologies, Memory Products, Network and Computer Storage
pp. 0268
Session 6.1: Energy Efficiency Caches and Multiport Cache Structures
Heather Hanson, The University of Texas at Austin
M.S. Hrishikesh, The University of Texas at Austin
Vikas Agarwal, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
Doug Burger, The University of Texas at Austin
pp. 0276
Parallel Cachelets (Abstract)
Deepak Limaye, Carnegie Mellon University
Ryan Rakvic, Intel Corporation
John P. Shen, Intel Corporation
pp. 0284
Session 6.2: Control by Simulation and On-line Checking
Session 6.3: CAD Algorithms for Physical Design
Fan Mo, University of California, Berkeley
Abdallah Tabbara, University of California, Berkeley
Robert K. Brayton, University of California, Berkeley
pp. 0322
Guang-Ming Wu, Nan-Hua University
Jai-Ming Lin, National Chiao Tung University
Mango C.-T. Chao, National Chiao Tung University
Yao-Wen Chang, National Taiwan University
pp. 0335
Panel Discussion
Session 7.1: Invited Session: Network Processors
Network Processing: Applications and Challenges
Payload+: Fast Pattern Matching and Routing for OC-48
Scaling Fully Programmable Network Processing to 10Gbps and Beyond
Session 7.2: Formal Methods for Property Verification and Equivalence Verification
Session 7.3: Hardware Representation
L.A. Smith King, College of the Holy Cross
Heather Quinn, Northeastern University
Miriam Leeser, Northeastern University
Demetris Galatopoullos, Northeastern University
Elias Manolakos, Northeastern University
pp. 0380
Session 8.1: Circuit Techniques
Sangyeun Cho, Samsung Electronics Co.
Wooyoung Jung, Samsung Electronics Co.
Yongchun Kim, Samsung Electronics Co.
Seh-Woong Jeong, Samsung Electronics Co.
pp. 0394
Azeez J. Bhavnagarwala, IBM T. J. Watson Research Center
Stephen Kosonocky, IBM T. J. Watson Research Center
James D. Meindl, Georgia Institute of Technology
pp. 0400
Session 8.2: DSP/Multimedia
Mihai Sima, Delft University of Technology and Philips Research
Sorin Cotofana, Delft University of Technology
Stamatis Vassiliadis, Delft University of Technology
Jos T.J. Van Eijndhoven, Philips Research
Kees Vissers, TriMedia Technologies
pp. 0425
Markus Lorenz, University of Dortmund, Germany
Rainer Leupers, University of Dortmund, Germany
Peter Marwedel, University of Dortmund, Germany
Thorsten Dräger, Technische Universit?t Dresden
Gerhard Fettweis, Technische Universit?t Dresden
pp. 0431
Session 8.3: Novel Architectures and ISA Extensions
Ying Zhao, Princeton University
Sharad Malik, Princeton University
Albert Wang, Tensilica Inc.
Conor F. Madigan, University of California at Berkeley
Matthew W. Moskewicz, University of California at Berkeley
pp. 0447
Hiroaki Kobayashi, Tohoku University
Yasumasa Saida, Tohoku University
Kentaro Sano, Tohoku University
Yoshiyuki Kaeriyama, Tohoku University
Tadao Nakamura, Tohoku University
Ken-ichi Suzuki, Miyagi National College of Technology
Nobuyuki Oba, IBM Japan, Ltd.
pp. 0462
S. Tomar, Pennsylvania State University
S. Kim, Pennsylvania State University
N. Vijaykrishnan, Pennsylvania State University
M. Kandemir, Pennsylvania State University
M. J. Irwin, Pennsylvania State University
pp. 0468
Poster Papers
Sadiq M. Sait, King Fahd University of Petroleum and Minerals
Habib Youssef, King Fahd University of Petroleum and Minerals
Junaid A. Khan, King Fahd University of Petroleum and Minerals
Aiman El-Maleh, King Fahd University of Petroleum and Minerals
pp. 0484
Witawas Srisa-an, Illinois Institute of Technology
Chia-Tien Dan Lo, Illinois Institute of Technology
J. Morris Chang, Illinois Institute of Technology
pp. 0493
Guang-Ming Wu, Nan-Hua University
Jai-Ming Lin, National Chiao Tung University
Yao-Wen Chang, National Taiwan University
pp. 0501
Myoung-Cheol Shin, Korea Advanced Institute of Science and Technology
Se-Hyeon Kang, Korea Advanced Institute of Science and Technology
In-Cheol Park, Korea Advanced Institute of Science and Technology
pp. 0511
J.L. White, Michigan State University
M.-J. Chung, Michigan State University
A.S. Wojcik, Michigan State University
T.E. Doom, Wright State University
pp. 0519
Halima El Naga, California State Polytechnic University
Jean-Luc Gaudiot, University of Southern California
pp. 0523
Kamran Zarrineh, SUN Microelectronics Millenium DFT Architecture Boston Design Center
Thomas A. Ziaja, SUN Microelectronics DFT Architecture Austin Design Center Austin
Amita va Majumdar, SUN Microelectronics DFT Architecture Sunnyvale Design Center Sunnyvale
pp. 0526
Pipat Reungsang, Iowa State University
Sun Kyu Park, Iowa State University
Gyungho Lee, Iowa State University
Seh-Woong Jeong, Samsung Electronics
Hyung-Lae Roh, Samsung Electronics
pp. 0530
Nikola Nedovic, University of California Davis
Marko Aleksic, University of California Davis
Vojin G. Oklobdzija, University of California Davis
pp. 0538
James D. Z. Ma, University of Wisconsin
Arvind Parihar, University of Wisconsin
Lei He, University of Wisconsin
pp. 0553
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