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2000 IEEE International Conference on Computer Design (ICCD'00)
Austin, Texas
September 17-September 20
ISBN: 0-7695-0801-4
Table of Contents
Keynote Address
Session 1.1: New Architectures, Chair: Mauricio Breternitz, Motorola
Session 1.2: Fault-Simulation and ATPG at Different Design Levels, Chair: Nur Touba, The University of Texas at Austin
Session 1.3: Advanced Design Techniques, Chair: Ken Shepard, Columbia University
Chulwoo Kim, University of Illinois at Urbana-Champaign
Jaesik Lee, University of Illinois at Urbana-Champaign
Kwang-Hyun Baek, University of Illinois at Urbana-Champaign
Eric Martina, University of Illinois at Urbana-Champaign
Sung-Mo (Steve) Kang, University of Illinois at Urbana-Champaign
pp. 59
S.W. Moore, University of Cambridge
G.S. Taylor, University of Cambridge
P.A. Cunningham, University of Cambridge
R.D. Mullins, University of Cambridge
P. Robinson, University of Cambridge
pp. 73
Session 2.1: Improving CPU Performance, Chair: Brian Grayson, Motorola
J. Morris Chang, Illinois Institute of Technology
Witawas Srisa-an, Illinois Institute of Technology
Chia-Tien Dan Lo, Illinois Institute of Technology
pp. 99
Session 2.2: Parasitic Modeling, Analysis, and Optimization, Chair: Tom Dillinger, Sun Microsystems
Tong Xiao, University of California at Santa Barbara
Malgorzata Marek-Sadowska, University of California at Santa Barbara
pp. 115
Session 2.3: Low Power and Arithmetic, Chair: Margarida Jacome, The University of Texas at Austin
Rafael Moreno, Universidad Complutense de Madrid
Luis Piñuel, Universidad Complutense de Madrid
Silvia del Pino, Universidad Complutense de Madrid
Francisco Tirado, Universidad Complutense de Madrid
pp. 147
Javier D. Bruguera, University of Santiago de Compostela
Toms Lang, University of California at Irvine
pp. 155
Deependra Talla, University of Texas at Austin
Lizy K. John, University of Texas at Austin
Viktor Lapinskii, University of Texas at Austin
Brian L. Evans, University of Texas at Austin
pp. 163
Session 3.1: Servers and Parallelism, Chair: Ruby Lee, Princeton University
Qiang Cao, University of Illinois at Urbana-Champaign
Josep Torrellas, University of Illinois at Urbana-Champaign
H. V. Jagadish, University of Illinois at Urbana-Champaign
pp. 175
John S. Seng, University of California at San Diego
Dean M. Tullsen, University of California at San Diego
George Z.N. Cai, Intel Corporation
pp. 199
Session 3.2: Circuit Optimization and Analysis, Chair: Shervin Hojat, IBM
Charles J. Alpert, IBM Austin Research Laboratory
R. Gopal Gandham, IBM Microelectronics
Jose L. Neves, IBM Microelectronics
Stephen T. Quay, IBM Microelectronics
pp. 221
Session 3.3: Logic Circuit Families, Chair: Shyh-Jye Jou, National Central University
S. Bobba, University of Illinois at Urbana-Champaign
I.N. Hajj, University of Illinois at Urbana-Champaign
pp. 235
Larry McMurchie, University of Washington
Su Kio, University of Washington
Gin Yee, University of Washington
Tyler Thorp, University of Washington
Carl Sechen, University of Washington
pp. 247
Session 4.1: Intelligent Memory, Chair: Steven Reinhardt, University of Michigan
Mark Oskin, University of California at Davis
Diana Keen, University of California at Davis
Justin Hensley, University of California at Davis
Lucian-Vlad Lita, University of California at Davis
Frederic T. Chong, University of California at Davis
pp. 276
Session 4.2: Processor Microarchitecture, Chair: Steve Furber, The University of Manchester
Jih-Ching Chiu, National Chiao Tung University
I-Huan Huang, National Chiao Tung University
Chung-Ping Chung, National Chiao Tung University
pp. 294
Session 4.3: Digital Logic Techniques, Chair: Barbara Chappell, Accelerant Networks
Hak-soo Yu, University of Texas at Austin
Songjun Lee, University of Texas at Austin
Jacob A. Abraham, University of Texas at Austin
pp. 311
Shyh-Jye Jou, National Central University
Hui-Hsuan Wang, National Central University
pp. 318
Nikola Nedovic, University of California at Davis
Vojin G. Oklobdzija, University of California at Davis
pp. 323
Session 5.1: Embedded Processors: Architecture and System-Design Issues, Chair: Ricardo Gonzales, Tensilica
Farinaz Koushanfar, University of California at Los Angeles
Miodrag Potkonjak, University of California at Los Angeles
Vandana Prabhu, Tensilica, Inc.
Jan M. Rabaey, University of California at Berkeley
pp. 603
S.B. Furber, University of Manchester
D.A. Edwards, University of Manchester
J.D. Garside, University of Manchester
pp. 329
Pavan Kumar, University of California at Los Angeles
Mani Srivastava, University of California at Los Angeles
pp. 343
Session 5.2: Floorplanning and Partitioning, Chair: Tim Burks, Magma Design Automation
Guang-Ming Wu, National Chiao Tung University
Yun-Chih Chang, National Chiao Tung University
Yao-Wen Chang, National Chiao Tung University
pp. 351
Koji Oohashi, Japan Advanced Institute of Science and Technology
Mineo Kaneko, Japan Advanced Institute of Science and Technology
Satoshi Tayu, Japan Advanced Institute of Science and Technology
pp. 370
Session 5.3: Basic Algorithms in Verification and Test, Chair: Yatin Hoskote, Intel
Session 6.1: Special Session: Advancements in DSP Architecture
Advancements in DSP Architecture
Sanjive Agarwala, Texas Instruments Incorporated
Charles Fuoco, Texas Instruments Incorporated
Tim Anderson, Texas Instruments Incorporated
Dave Comisky, Texas Instruments Incorporated
Christopher Mobley, Texas Instruments Incorporated
pp. 408
Dave Comisky, Texas Instruments, Incorporated
Sanjive Agarwala, Texas Instruments, Incorporated
Charles Fuoco, Texas Instruments, Incorporated
pp. 414
Session 6.2: Advanced Architectural Design and Synthesis, Chair: Edward Grochowski, Intel
Makiko Itoh, Osaka University
Shigeaki Higaki, Osaka University
Yoshinori Takeuchi, Osaka University
Akira Kitajima, Osaka University
Masaharu Imai, Osaka University
Jun Sato, Tsuruoka National College of Technology
Akichika Shiomi, Shizuoka University
pp. 430
Satish Pillai, University of Texas at Austin
Margarida Jacome, University of Texas at Austin
pp. 437
Dinesh Ramanathan, University of California at Irvine
Rajesh Gupta, University of California at Irvine
Ray Roth, University of California at Santa Clara
pp. 445
Session 6.3: Application and Case Studies in Test and Verification, Chair: Carl Pixley, Motorola
Hoon Choi, Samsung Electronics - Korea
Myung-Kyoon Yim, Samsung Electronics - Korea
Jae-Young Lee, Samsung Electronics - Korea
Byeong-Whee Yun, Samsung Electronics - Korea
Yun-Tae Lee, Samsung Electronics - Korea
pp. 453
Invited Paper
Hilary J. Kahn, University of Manchester
R.B.E. Napper, University of Manchester
pp. 481
Session 7.1: Logic Optimization, Chair: Chin-Long Wey, Michigan State University
Subarnarekha Sinha, University of California at Berkley
Sunil P. Khatri, University of California at Berkley
Robert K. Brayton, University of California at Berkley
Alberto L. Sangiovanni-Vincentelli, University of California at Berkley
pp. 494
Per Lindgren, Lule? University of Technology
Rolf Drechsler, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
pp. 504
Session 7.2: High Level Specification and Synthesis, Chair: Pranav Ashar, NEC
F. Hessel, TIMA Laboratory and Catholic University of Porto Alegre
P. Coste, TIMA Laboratory
G. Nicolescu, TIMA Laboratory
P. LeMarrec, TIMA Laboratory
N. Zergainoh, TIMA Laboratory
A. Jerraya, TIMA Laboratory
pp. 525
Poster Sessions
A. Benso, Politecnico di Torino
S. Di Carlo, Politecnico di Torino
S. Chiusano, Politecnico di Torino
P. Prinetto, Politecnico di Torino
F. Ricciato, Politecnico di Torino
M. Lobetti Bodoni, Siemens Information and Communication Networks S.p.A.
M. Spadari, LSI Logic
pp. 539
Haizhou Chen, Marvell Semiconductor, Inc.
Bing Lu, University of Minnesota
Ding-Zhu Du, University of Minnesota
pp. 541
Steve Haynal, University of California at Santa Barbara
Forrest Brewer, University of California at Santa Barbara
pp. 552
Toru Hiyama, Hitachi, Ltd.
Yuko Ito, Hitachi, Ltd.
Satoru Isomura, Hitachi, Ltd.
Kazunobu Nojiri, Hitachi Information Technology Co., Ltd.
Eijiro Maeda, Hitachi Information Technology Co., Ltd.
pp. 556
Yoochang Jung, University of Washington
Stefan G. Berg, University of Washington
Donglok Kim, University of Washington
Yongmin Kim, University of Washington
pp. 559
H. Lavana, North Carolina State University
F. Brglez, North Carolina State University
R. Reese, Mississippi State University
G. Konduri, Massachusetts Institute of Technology
A. Chandrakasan, Massachusetts Institute of Technology
pp. 567
R. Maestre, Universidad Complutense
M. Fernandez, Universidad Complutense
R. Hermida, Universidad Complutense
F.J. Kurdahi, University of California at Irvine
N. Bagherzadeh, University of California at Irvine
H. Singh, University of California at Irvine
pp. 575
Afzal Malik, Motorola, Incorporated
Bill Moyer, Motorola, Incorporated
Dan Cermak, Motorola, Incorporated
pp. 577
Srivaths Ravi, Princeton University
Niraj K. Jha, Princeton University
Indradeep Ghosh, Fujitsu Labs of America
Vamsi Boppana, Fujitsu Labs of America
pp. 591
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