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1999 IEEE International Conference on Computer Design (ICCD'99)
Austin, Texas
October 10-October 13
ISBN: 0-7695-0406-X
Table of Contents
Session 1.1.1: Keynote Address
Kurt. Keutzer, University of California at Berkeley
A. Richard Newton, University of California at Berkeley
pp. 14
Session 1.3.1: Embedded Tutorial
Session 1.3.2: Applied Verification Techniques, Co-Chairs: Carl Pixley, Motorola, USA and Warren Hunt, IBM Austin Research Laboratory, USA
Session 1.3.3: Computer Arithmetic, Chair: Kevin Nowka, IBM Austin Research Laboratory, USA
Sumio Morioka, IBM Research, Tokyo Research Laboratory
Yasunao Katayama, IBM Research, Tokyo Research Laboratory
pp. 60
Lunch Presentation
Evolution of DSP Architecture
Session 1.4.1: Machines and Characterization, Chair: Chris Newburn, Intel, USA
Jeff Scott, Motorola Incorporated
Lea Hwang Lee, Motorola Incorporated
Ann Chin, Motorola Incorporated
John Arends, Motorola Incorporated
Bill Moyer, Motorola Incorporated
pp. 94
Qiang Cao, University of Illinois at Urbana-Champaign
Josep Torrellas, University of Illinois at Urbana-Champaign
Pedro Trancoso, Intercollege Limassol
Josep Lluis Larriba-Pey, Universitat Politecnica de Catalunya
Bob Knighten, Intel Corporation
Youjip Won, Intel Corporation
pp. 108
Session 1.4.2: Power and Noise Considerations in Microprocessor Design, Chair: Priyadarsan Patra, Intel, USA
Session 1.4.3: Architectures for Embedded Systems, Chair: Tom Truman, Lucent Bell Laboratories, USA
David Landis, Pennsylvania State University
Paul Hulina, Pennsylvania State University
Scott Deno, Pennsylvania State University
Luke Roth, Pennsylvania State University
Lee Coraor, Pennsylvania State University
pp. 146
Session 1.4.4: Built-In Self Test, Chair: Cheng-Ping Wang, Texas Instruments, USA
Session 1.5.1: Intelligent Memory, Chair: Doug Burger, The University of Texas at Austin, USA
Yi Kang, University of Illinois at Urbana Champaign
Wei Huang, University of Illinois at Urbana Champaign
Seung-Moon Yoo, University of Illinois at Urbana Champaign
Diana Keen, University of Illinois at Urbana Champaign
Zhenzhou Ge, University of Illinois at Urbana Champaign
Vinh Lam, University of Illinois at Urbana Champaign
Josep Torrellas, University of Illinois at Urbana Champaign
pp. 192
Session 1.5.2: Performance and Area Optimization, Chair: Shantanu Ganguly, Intel, USA
I-Min Liu, University of Texas at Austin
Adnan Aziz, University of Texas at Austin
D.F. Wong, University of Texas at Austin
Hai Zhou, Synopsys Incorporated
pp. 210
Session 1.5.3: VLSI Implementation of Arithmetic Circuits, Chair: Magdy Abidir, Motorola, USA
Alberto Nannarelli, University of California at Irvine
Tomas Lang, University of California at Irvine
pp. 236
Bong-Il Park, Korea Advanced Institute of Science and Technology
In-Cheol Park, Korea Advanced Institute of Science and Technology
Chong-Min Kyung, Korea Advanced Institute of Science and Technology
pp. 243
Session 1.5.4: Design Convergence, Chair: Georg Pelz, Gerhard-Mercator University GH, Duisberg, Germany
Narendra Shenoy, Synopsys Incorporated
Mahesh Iyer, Synopsys Incorporated
Robert Damiano, Synopsys Incorporated
Kevin Harer, Synopsys Incorporated
Hi-Keung Ma, Synopsys Incorporated
Paul Thilking, 3DFX International
pp. 250
Wilm Donath, IBM T.J Watson Research Center
Prabhakar Kudva, IBM T.J Watson Research Center
Lakshmi Reddy, IBM Server Division
pp. 258
Martin Kuhlmann, University of Minnesota
Sachin S. Sapatnekar, University of Minnesota
Keshab K. Parhi, University of Minnesota
pp. 266
Session 1.6: Poster Presentations
Hasan Cam, King Fahd University of Petroleum and Minerals
Mostafa Abd-El-Barr, King Fahd University of Petroleum and Minerals
Sadiq M. Sait, King Fahd University of Petroleum and Minerals
pp. 274
Avinash K. Gautam, Texas Instruments India Limited
V. Visvanathan, Indian Institute of Science
S.K. Nandy, Indian Institute of Science
pp. 285
G.S Samudra, National University of Singapore
H.M. Chen, National University of Singapore
D.S.H. Chan, National University of Singapore
Yaacob Ibrahim, National University of Singapore
pp. 289
Kyoung-Mook Lim, Samsung Electronics Co. and KAIST
Seh-Woong Jeong, Samsung Electronics Co. and KAIST
Yong-Chun Kim, Samsung Electronics Co. and KAIST
Seung-Jae Jeong, Samsung Electronics Co. and KAIST
Hong-Kyu Kim, Samsung Electronics Co. and KAIST
Yang-Ho Kim, Samsung Electronics Co. and KAIST
Bong-Young Chung, Samsung Electronics Co. and KAIST
Hyung-Lae Roh, Samsung Electronics Co. and KAIST
H.S. Yang, Samsung Electronics Co. and KAIST
pp. 299
Shuenn-Shi Chen, National Taiwan University
Jong-Jang Chen, National Taiwan University
Sao-Jie Chen, National Taiwan University
Chia-Chun Tsai, National Taipei University of Technology
pp. 303
Per Lindgren, Lule University of Technology
Rolf Drechsler, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
pp. 307
Michael Shyu, National Chiao Tung University
Yu-Dong Chang, National Chiao Tung University
Guang-Ming Wu, National Chiao Tung University
Yao-Wen Chang, National Chiao Tung University
pp. 311
Session 1.7: Panel Discussion
Iteration-Free Timing Closure
Session 2.1: Plenary
MicroProcessor Architecture; Trends and Directions
Session 2.2.1: System Level Issues, Chair: Margarida Jacome, The University of Texas at Austin, USA
Avinask K. Gautam, Texas Instruments India Ltd
Jagadish Rao, Texas Instruments India Ltd
Karthikeyan Madathil, Texas Instruments India Ltd
Vilesh Shah, Texas Instruments India Ltd
H Udayakumar, Texas Instruments India Ltd
Amitabh Menon, Texas Instruments India Ltd
Subash Chandar, Texas Instruments India Ltd
pp. 340
Session 2.2.2: Compilers and Algorithms, Chair: Steve Keckler, The University of Texas at Austin, USA
Nikolaos Bellas, University of Illinois at Urbana-Champaign
Ibrahim Hajj, University of Illinois at Urbana-Champaign
Constantine Polychronopoulos, University of Illinois at Urbana-Champaign
George Stamoulis, University of Illinois at Urbana-Champaign
pp. 378
Priyadarshan Kolte, Motorola, Incorporated
Roger Smith, Motorola, Incorporated
Wen Su, Motorola, Incorporated
pp. 384
Session 2.2.3: Test Generation and Delay Testing, Chair: Karim Arabi, Ecole de Technologie Superieure (ETS), Canada
Session 2.3.1: Microarchitecture, Chair: Andrew Pleszkun, University of Colorado, USA
Chi-Hung Chi, National University of Singapore
Jun-Li Yuan, National University of Singapore
pp. 436
Akhilesh Tyagi, Iowa State University
Hon-Chi Ng, Iowa State University
Prasant Mohapatra, Michigan State University
pp. 442
Session 2.3.2: Efficient State-Space Exploration, Chair: Anna Slobodova, Compaq, USA
Rob Sumners, University of Texas At Austin
Jayanta Bhadra, University of Texas At Austin
Jacob Abraham, University of Texas At Austin
pp. 452
Session 2.3.3: Clocking and Analog Circuit Prototyping, Chair: Rajesh Galivanche, Intel, USA
Matthew E. Becker, Massachusetts Institute of Technology
Thomas F. Knight, Jr., Massachusetts Institute of Technology
pp. 489
Session 2.3.4: Embedded Tutorial, Organizer and Chair: Andreas Both, Motorola Semiconductor Products Sector, USA
Invited Session 2.4.1: Digital Signal Processors, Organizer and Chair: Ken Shepard, Columbia University, USA
Uming Ko, Texas Instruments Incorporated
Mike McMahan, Texas Instruments Incorporated
Edgar Auslander, Texas Instruments Incorporated
pp. 516
Nagaraj Ns, Texas Instruments Incorporation
Frank Cano, Texas Instruments Incorporation
Sudha Thiruvengadam, Texas Instruments Incorporation
Deepak Kapoor, Texas Instruments Incorporation
pp. 521
Session 2.4.2: Caching Approaches, Chair: Mauricio Breternitz, Motorola, USA
Peter van Vleet, University of Washington
Eric Anderson, University of Washington
Lindsay Brown, University of Washington
Jean-Loup Baer, University of Washington
Anna Karlin, University of Washington
pp. 528
Session 2.4.3: CMOS Circuit Design Techniques, Chair: Sharad Mehrotra, IBM, USA
Tyler Thorp, University of Washington
Gin Yee, University of Washington
Carl Sechen, University of Washington
pp. 569
J.V. Tran, IBM Corporation
F. Mounes-Toussi, IBM Corporation
S.N. Storino, IBM Corporation
D.L. Stasiak, IBM Corporation
pp. 573
Session 3.1: Plenary
Invited Session 3.2.1
The TriMedia CPU64 VLIW Media Processor
A.K. Riemens, Philips Research Labs
K.A. Vissers, Philips Research Labs
R.J. Schutten, Philips Research Labs
G.J. Hekstra, Philips Research Labs
G.D. La Hei, Philips Research Labs
F.W. Sijstermans, Philips Semiconductors TriMedia
pp. 580
J.T.J. Van Eijndhoven, Philips Research Laboratories Eindhoven
K.A. Vissers, Philips Research Laboratories Eindhoven
E.J.D. Pol, Philips Research Laboratories Eindhoven
P. Struik, Philips Research Laboratories Eindhoven
R.H.J. Bloks, Philips Research Laboratories Eindhoven
P. van der Wolf, Philips Research Laboratories Eindhoven
H.P.E. Vranken, Philips Research Laboratories Eindhoven
F.W. Sijstermans, Philips Semiconductors
M.J.A. Tromp, Philips Semiconductors
A.D. Pimentel, University of Amsterdam
pp. 586
E.J.D. Pol, Philips Research Laboratories Eindhoven
B.J.M. Aarts, Philips Research Laboratories Eindhoven
J.T.J. Van Eindhoven, Philips Research Laboratories Eindhoven
P. Struik, Philips Research Laboratories Eindhoven
P. van der Wolf, Philips Research Laboratories Eindhoven
F.W. Sijstermans, Philips Semiconductors
M.J.A. Tromp, Philips Semiconductors
J.W. van de Waerdt, Philips Semiconductors
pp. 593
G.J. Hekstra, Philips Research Labs, Eindhoven
G.D. La Hei, Philips Research Labs, Eindhoven
P. Bingley, Philips Research Labs, Eindhoven
F.W. Sijstermans, Philips Semiconductors
pp. 599
Session 3.2.2: Logic Synthesis, Chair: Ken Shepard, Columbia University, USA
Pradip K. Jha, IBM EDA Lab
Steven Barnfield, IBM EDA Lab
John Weaver, IBM EDA Lab
Rudra Mukherjee, ViewLogic Systems Incorporated
Reinaldo A. Bergamaschi, IBM T. J. Watson Research Center
pp. 614
Rupesh S. Shelar, Silicon Automation Systems Limited
Madhav P. Desai, Indian Institute of Technology at Bombay.
H. Narayanan, Indian Institute of Technology at Bombay.
pp. 620
Congguang Yang, University of Massachusetts at Amherst
Maciej Ciesielski, University of Massachusetts at Amherst
Vigyan Singhal, Cadence Berkeley Laboratory
pp. 626
Session 3.2.3: Hardware Software Partitioning and Synthesis, Chair: Miodrag Potkonjak, University of California at Los Angeles, USA
Felice Balarin, Cadence Berkeley Labs Cadence Design Systems
Massimiliano Chiodo, Cadence Berkeley Labs Cadence Design Systems
pp. 634
Xiaohan Zhu, University of California at San Diego
Bill Lin, University of California at San Diego
pp. 646
Gang Quan, University of Notre Dame
Sharon (Xiaobo) Hu, University of Notre Dame
Garrison Greenwood, Western Michigan University
pp. 652
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