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1999 IEEE International Conference on Computer Design (ICCD'99)
Customization of a CISC Processor Core for Low-Power Applications
Austin, Texas
October 10-October 13
ISBN: 0-7695-0406-X
| ASCII Text | x | ||
| You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung, "Customization of a CISC Processor Core for Low-Power Applications," 2012 IEEE 30th International Conference on Computer Design (ICCD), pp. 152, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999. | |||
| BibTex | x | ||
| @article{ 10.1109/ICCD.1999.808420, author = {You-Sung Chang and Bong-Il Park and In-Cheol Park and Chong-Min Kyung}, title = {Customization of a CISC Processor Core for Low-Power Applications}, journal ={2012 IEEE 30th International Conference on Computer Design (ICCD)}, volume = {0}, year = {1999}, issn = {1063-6404}, pages = {152}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808420}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE 30th International Conference on Computer Design (ICCD) TI - Customization of a CISC Processor Core for Low-Power Applications SN - 1063-6404 SP EP A1 - You-Sung Chang, A1 - Bong-Il Park, A1 - In-Cheol Park, A1 - Chong-Min Kyung, PY - 1999 KW - Low-power-design KW - CISC-processor KW - Complex-instruction KW - Microcode KW - ROM-compile VL - 0 JA - 2012 IEEE 30th International Conference on Computer Design (ICCD) ER - | |||
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully utilizing the microcode-based control scheme, that is one of the most characterizing features of a CISC processor. The optimization process includes two key techniques, generation of application-specific complex instructions (ASCI) and low-power-oriented microcode-ROM compilation, which independently operate at the two different levels of optimization.As a means of architectural level of optimization, application-specific complex instructions are generated so as to reduce the activities of fetch and decode units, and in the point of physical level of optimization, the microcode-ROM is compiled to reduce the bit-line toggling for each microcode-ROM access. Our experimental results based on transistor-level simulation show the proposed techniques can jointly reduce the total power consumption of the CISC processor core by up to 41%.
Index Terms:
Low-power-design, CISC-processor, Complex-instruction, Microcode, ROM-compile
Citation:
You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung, "Customization of a CISC Processor Core for Low-Power Applications," iccd, pp.152, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999
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