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1998 IEEE International Conference on Computer Design (ICCD'98)
Austin, Texas
October 05-October 05
ISBN: 0-8186-9099-2
Table of Contents
Session 1.1: Keynote Speech
Deep Blue: The IBM Chess Machine
Session 1.2: Plenary
Making Computer-Dependent Airplanes Safer through Formal Methods
Special Invited Session 1.3.1: A Prototype 1 GHz PowerPC Microprocessor
Session 1.3.2: Built-in-Self-Test
Session 1.3.3: Design Optimization
Session 1.3.4: Power and Noise Estimation and Optimization
Lunch Presentation
The Transformation of the IBM S/390 Enterprise Servers
Special Invited Session 1.4.1: The Alpha 21264 Microprocessor
Emily Shriver, Compaq Computer Corporation
Dale Hall, Compaq Computer Corporation
Nevine Nassif, Compaq Computer Corporation
Nadir Rahman, Compaq Computer Corporation
Nick Rethman, Compaq Computer Corporation
Gill Watt, Compaq Computer Corporation
Jim Farrell, Compaq Computer Corporation
pp. 96
Session 1.4.2: Technical Forum
Technology Challenges for Design and Computer-Aided Design of Digital Integrated Circuits
Session 1.4.3: Arithmetic I
Session 1.4.4: Logic Synthesis
Poster Session 1.5
Ran Ginosar, Technion-Israel Institute of Technology
Rakefet Kol, Technion-Israel Institute of Technology
pp. 188
Jianping Lu, Concordia University
Sofiene Tahar, Concordia University
Dan Voicu, University of Montreal
Xiaoyu Song, University of Montreal
pp. 195
ShenHui Wu, Colorado State University
Yashwant K. Malaiya, Colorado State University
Anura P. Jayasumana, Colorado State University
pp. 221
Session 1.6.1: Panel
Formal Verification ¾ "Peripheral" or "Indispensable"?
Session 2.1: Plenary
Architects Should not Write Checks that Design Teams Can't Cash
Special Invited Session 2.2.1: The ARM Microprocessor
S.B. Furber, The University of Manchester,
J. D. Garside, The University of Manchester,
D.A. Gilbert, Cogency Technology, Inc.,
pp. 247
Session 2.2.2: Technical Forum
Dynamically and Partially Reconfigurable Architectures: New Opportunities and Challenges
Embedded Tutorial
Noise and Signal Integrity Issues in Deep Submicron Design
Session 2.2.4: High Performance Design Techniques
AltiVec: Motorola's High Performance Vector Parallel Processing Expansion to the PowerPC Architecture
Session 2.3.1: Arithmetic II
Hyun-Chul Shin, Korea Advanced Institute of Science and Technology
Jin-Aeon Lee, Korea Advanced Institute of Science and Technology
Lee-Sup Kim, Korea Advanced Institute of Science and Technology
pp. 286
Session 2.3.2: Practical Functional Verification
Nina Saxena, University of Texas at Austin
Jacob Abraham, University of Texas at Austin
pp. 314
Session 2.3.3: System Performance Issues
Mohamad Mansour, American University of Beirut
Ayman Kayssi, American University of Beirut
pp. 334
Session 2.3.4: Asynchronous Design Techniques
Session 2.4.1: Cache and Memory Systems
Edward S. Tam, The University of Michigan
Jude A. Rivers, The University of Michigan
Vijayalakshmi Srinivasan, The University of Michigan
Gary S. Tyson, The University of Michigan
Edward S. Davidson, The University of Michigan
pp. 368
Session 2.4.2: Timing and Synthesis Verification
Session 2.4.3: Low Power/High Efficiency Networks
Alberto Nannarelli, University of California, Irvine
Tomas Lang, University of California, Irvine
pp. 420
Kenneth Y. Yun, University of California, San Diego
Kevin W. James, University of California, San Diego
Robert Fairlie-Cuninghame, University of California, San Diego
Rene L. Cruz, University of California, San Diego
Supratik Chakraborty, Stanford University
pp. 427
Session 2.4.4: High-Level Synthesis
Session 2.5.1: Panel
Legacy Instruction Sets: Aging Like Fine Wine, or Rusting Like Old Buicks?
Dinner Presentation
Venture Capital and the Start-up Company
Session 3.1: Plenary
The Unbundling of the Semiconductor Industry
Session 3.2.1: Embedded Tutorial
Session 3.2.2: VLIW and Parallel Processing
Andrew Chang, Stanford University
William J. Dally, Stanford University
Stephen W. Keckler, Stanford University
Nicholas P. Carter, Stanford University
Whay S. Lee, Massachusetts Institute of Technology
pp. 474
Session 3.2.3: ATPG
Paulo F. Flores, Instituto Superior Tecnico/INESC
Horacio C. Neto, Instituto Superior Tecnico/INESC
Joao P. Marques Silva, Instituto Superior Tecnico/INESC
pp. 510
Session 3.2.4: Timing and Power Analysis
Session 3.3.1: Performance Analysis and Microarchitecture
Lizy John, The University of Texas at Austin
Yin Teh, The University of Texas at Austin
Francis Matus, The University of Texas at Austin
Craig Chase, The University of Texas at Austin
pp. 550
Lucian Codrescu, Georgia Institute of Technology
D. Scott Wills, Georgia Institute of Technology
pp. 558
Session 3.3.2: Mixed Signal Testing
Session 3.3.3: Co-Design
Sadiq M. Sait, King Fahd University of Petroleum & Minerals
Walling R. Cyre, Virginia Tech
pp. 596
Session 3.3.4: Place and Route
Aiguo Lu, LSI Logic Corporation
Hans Eisenmann, Technical University of Munich
Guenter Stenz, Technical University of Munich
Frank M. Johannes, Technical University of Munich
pp. 616
Lixin Su, University of California at Berkeley
Wray Buntine, University of California at Berkeley
Richard A. Newton, University of California at Berkeley
Bradley S. Peters, University of California at Berkeley
pp. 622
Kai Zhu, Triscend Corp.
Yao-Wen Chang, National Chiao Tung University
D.F. Wong, University of Texas at Austin
pp. 628
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