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1997 IEEE International Conference on Computer Design (ICCD'97)
Austin, TX
October 12-October 15
ISBN: 0-8186-8206-X
Table of Contents
Session 1.1: Keynote Speech
David Patterson, Computer Science Division University of California, Berkeley CA
Krste Asanovic, Computer Science Division University of California, Berkeley CA
Aaron Brown, Computer Science Division University of California, Berkeley CA
Richard Fromm, Computer Science Division University of California, Berkeley CA
Jason Golbus, Computer Science Division University of California, Berkeley CA
Benjamin Gribstad, Computer Science Division University of California, Berkeley CA
Kimberly Keeton, Computer Science Division University of California, Berkeley CA
Christoforos Kozyrakis, Computer Science Division University of California, Berkeley CA
David Martin, Computer Science Division University of California, Berkeley CA
Stylianos Perissakis, Computer Science Division University of California, Berkeley CA
Randi Thomas, Computer Science Division University of California, Berkeley CA
Noah Treuhaft, Computer Science Division University of California, Berkeley CA
Katherine Yelick, Computer Science Division University of California, Berkeley CA
pp. 2
Session 1.2: CAD Plenary
Session 1.3.1: Special Session: Industrial Applications of Formal Verification
G.P. Bischoff, Digital Semicond., Digital Equip. Corp., Hudson, MA, USA
K.S. Brace, Digital Semicond., Digital Equip. Corp., Hudson, MA, USA
S. Jain, Digital Semicond., Digital Equip. Corp., Hudson, MA, USA
R. Razdan, Digital Semicond., Digital Equip. Corp., Hudson, MA, USA
pp. 16
J. Savir, Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
pp. 37
N.A. Touba, Center for Reliable Comput., Stanford Univ., CA, USA
E.J. McCluskey, Center for Reliable Comput., Stanford Univ., CA, USA
pp. 54
Session 1.3.3: Simulation and Power Estimation
Serban Bruma, CAS Group, Technical University DELFT
Ralph H.J.M. Otten, CAS Group, Technical University DELFT
pp. 62
Hoon Choi, Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Seung Ho Hwang, Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
pp. 68
B. Chen, Synopsys Inc., Mountain View, CA, USA
I. Nedelchev, Synopsys Inc., Mountain View, CA, USA
pp. 74
Session 1.3.4: Branch Prediction
I.-C.K. Chen, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Chih-Chieh Lee, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
M. Postiff, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
T. Mudge, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 88
Session 1.4.1: New Techniques for Gate-Sizing and Retiming
R. Haddad, Synopsys Inc., Mountain View, CA, USA
L.P.P.P. van Ginneken, Synopsys Inc., Mountain View, CA, USA
N. Shenoy, Synopsys Inc., Mountain View, CA, USA
pp. 110
Peichen Pan, Dept. of Electr. & Comput. Eng., Clarkson Univ., Potsdam, NY, USA
pp. 116
A.K. Karandikar, Intel Corp., Folsom, CA, USA
Peichen Pan, Intel Corp., Folsom, CA, USA
C.L. Liu, Intel Corp., Folsom, CA, USA
pp. 122
Session 1.4.2: Circuit Modeling
R. Mehrotra, Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram, Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Xunwei Wu, Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 130
A.C. Cangellaris, Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
W. Pinello, Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
A. Ruehli, Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
pp. 136
A. Dharchoudhury, High Performance Design Technology, Unified Design Systems Lab
D. Blaauw, High Performance Design Technology, Unified Design Systems Lab
J. Norton, High Performance Design Technology, Unified Design Systems Lab
S. Pullela, High Performance Design Technology, Unified Design Systems Lab
J. Dunning, Somerset Design Center, Motorola Inc.
pp. 143
Session 1.4.3: Novel Architectures
Xingbin Zhang, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
A. Dasdan, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
M. Schulzt, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
R.K. Gupta, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
A.A. Chien, Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 150
Minoru Inamori, NTT Optical Network Systems Laboratories
Kenji Ishii, NTT Optical Network Systems Laboratories
Akihiro Tsutsui, NTT Optical Network Systems Laboratories
Kazuhiro Shirakawa, NTT Optical Network Systems Laboratories
Hiroshi Nakada, NTT Optical Network Systems Laboratories
Toshiaki Miyazaki, NTT Optical Network Systems Laboratories
pp. 157
Short Papers
J.A.J. Leijten, Philips Res. Lab., Eindhoven, Netherlands
J.L. van Meerbergen, Philips Res. Lab., Eindhoven, Netherlands
A.H. Timmer, Philips Res. Lab., Eindhoven, Netherlands
J.A.G. Jess, Philips Res. Lab., Eindhoven, Netherlands
pp. 164
Session 1.4.4: Low Power Architectures
R.V.K. Pillai, Concordia Univ., Montreal, Que., Canada
D. Al-Khalili, Concordia Univ., Montreal, Que., Canada
A.J. Al-Khalili, Concordia Univ., Montreal, Que., Canada
pp. 178
Yun-Nan Chang, Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
J.H. Satyanarayana, Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi, Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 186
K. Muhammad, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 196
Session 1.5.1: Timing Optimization for Deep Submicron Technology
H. Vaishnav, Cadence Design Syst. Inc., San Jose, CA, USA
Chi-Keung Lee, Cadence Design Syst. Inc., San Jose, CA, USA
M. Pedram, Cadence Design Syst. Inc., San Jose, CA, USA
pp. 211
A.D. Mehta, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Yao-Ping Chen, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
N. Menezes, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
D.F. Wong, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
L.T. Pileggi, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 217
R. Arunachalam, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
F. Dartu, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
L.T. Pileggi, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 224
Session 1.5.2: Special Session: The G4 S/390 Microprocessor
K.L. Shepard, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
S. Carey, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D.K. Beece, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R. Hatch, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
G. Northrop, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 232
C.F. Webb, IBM Corp., Poughkeepsie, NY, USA
J.S. Liptay, IBM Corp., Poughkeepsie, NY, USA
pp. 241
J. Warnock, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
L. Sigal, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
B. Curran, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Y. Chan, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 247
Session 1.5.3: Multiprocessor Communication
R. Castaneda, Texas Univ., San Antonio, TX, USA
Xiaodong Zhang, Texas Univ., San Antonio, TX, USA
J.M. Hoover, Jr., Texas Univ., San Antonio, TX, USA
pp. 258
H. Oi, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
N. Ranganathan, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 267
M. Kozuch, Dept. of Electr. Eng., Princeton Univ., NJ, USA
W. Wolf, Dept. of Electr. Eng., Princeton Univ., NJ, USA
A. Wolfe, Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 273
W. K. Luk, IBM Thomas J. Watson Research Center
W. Hwang, IBM Thomas J. Watson Research Center
P. Xiao, IBM Thomas J. Watson Research Center
R. Joshi, IBM Thomas J. Watson Research Center
Y. Katayama, IBM Research, Tokyo Research Laboratory
A. Satoh, IBM Research, Tokyo Research Laboratory
S. Munetoh, IBM Research, Tokyo Research Laboratory
M. Wordeman, IBM Semiconductor Research and Development Center
T. Kirihata, IBM Semiconductor Research and Development Center
H. Wong, IBM Semiconductor Research and Development Center
B. El-Kareh, IBM Power PC Microprocessor Development
pp. 279
Session 1.5.4: Asynchronous Architectures
A. Takamura, Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
M. Kuwako, Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
M. Imai, Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
T. Fujii, Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
M. Ozawa, Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
I. Fukasaku, Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
Y. Ueno, Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
T. Nanya, Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
pp. 288
David S. Bormann, Imperial College of Science, Technology and Medicine University of London
Peter Y. K. Cheung, Imperial College of Science, Technology and Medicine University of London
pp. 307
Session 1.6.1
Session 1.6.2
Session 2.1 Design and Test Plenary
Session 2.2.1: Binary Decision Diagrams
S. Jha, Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
Y. Lu, Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
M. Minea, Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
E.M. Clarke, Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 332
R.K. Ranjan, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
W. Gosti, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincenteili, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 344
Zhongcheng Li, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Yuhong Zhao, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Yinghua Min, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 352
Session 2.2.2: Advanced Test Topics
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 360
D. Kagaris, Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
S. Tragoudas, Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
D. Karayiannis, Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 366
R.D. Blanton, Center for Electron. Design Autom., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.P. Hayes, Center for Electron. Design Autom., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 372
Session 2.2.3: Embedded Software and Systems
Yanbing Li, Princeton University
Wayne Wolf, Princeton University
Miodrag Potkonjak, Department of Computer Science, UCLA
pp. 388
A. Allara, Central Res. Lab., ITALTEL-SIT, Italy
S. Filipponi, Central Res. Lab., ITALTEL-SIT, Italy
W. Fornaciari, Central Res. Lab., ITALTEL-SIT, Italy
F. Salice, Central Res. Lab., ITALTEL-SIT, Italy
D. Sciuto, Central Res. Lab., ITALTEL-SIT, Italy
pp. 400
Session 2.2.4: Low Power Issues
C.S. Patel, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
S.M. Chai, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
S. Yalamanchili, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
D.E. Schimmel, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 408
P. Soderquist, Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
M. Leeser, Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
pp. 417
J.A. Tierno, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
P. Kudva, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 423
Wai-Chi Fang, Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
Guang Yang, Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
B. Pain, Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
B.J. Sheu, Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
pp. 429
Session 2.3.1: Formal Verification Methods
A.J. Hu, Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
M. Fujita, Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
C. Wilson, Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
pp. 438
Jawahar Jain, Fujitsu Laboratories of America
M. Fujita, Fujitsu Laboratories of America
Amit Narayan, University of California, Berkeley
A. Sangiovanni-Vincentelli, University of California, Berkeley
pp. 445
W. Canfield, CAE, Austin, TX, USA
E.A. Emerson, CAE, Austin, TX, USA
A. Saha, CAE, Austin, TX, USA
pp. 455
Session 2.3.2: Mixed Signal Design and Test
Cheng-Ping Wang, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Chin-Long Wey, Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 468
Jin Chen, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
A. Ramachandran, Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
pp. 474
Session 2.3.3: FPGA Design
J. Stohmann, Inst. of Microelectron. Syst., Hannover Univ., Germany
E. Barke, Inst. of Microelectron. Syst., Hannover Univ., Germany
pp. 489
Wai-Kei Mak, University of Texas at Austin
D. F. Wong, University of Texas at Austin
pp. 496
Session 2.3.4: Cache Technology I
Chenxi Zhang, Changsha Inst. of Technol., Hunan, China
Xiaodong Zhang, Changsha Inst. of Technol., Hunan, China
Yong Yan, Changsha Inst. of Technol., Hunan, China
pp. 504
L.K. John, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
A. Subramanian, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 510
J.A. Rivers, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
E.S. Tam, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
E.S. Davidson, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 519
Session 2.4.1: Embedded Tutorial
Session 2.4.2: Fault Diagnosis
W.A. Moreno, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
F.J. Falquez, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
J.R. Samson, Jr., Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
T. Smith, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
pp. 544
C. Bolchini, Dipt. di Elettronica, Politecnico di Milano, Italy
D. Sciuto, Dipt. di Elettronica, Politecnico di Milano, Italy
F. Salice, Dipt. di Elettronica, Politecnico di Milano, Italy
pp. 555
Session 2.4.3: Special Session: Low Power Design Issues
Session 2.4.4: Cache Technology II
Kih-Kwon Peir, CISE Dept., Florida Univ., Gainesville, FL, USA
W.W. Hsu, CISE Dept., Florida Univ., Gainesville, FL, USA
H. Young, CISE Dept., Florida Univ., Gainesville, FL, USA
S. Ong, CISE Dept., Florida Univ., Gainesville, FL, USA
pp. 578
P. Ranjan Panda, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
H. Nakamura, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
N.D. Dutt, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
A. Nicolau, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 587
I-Cheng K. Chen, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Chih-Chieh Lee, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
T.N. Mudge, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 593
Session 3.1: Architecture & Algorithm Plenary
R.H. Katz, Div. of Comput. Sci., California Univ., Berkeley, CA, USA
pp. 604
Session 3.2.1: Layout Partitioning and Synthesis
X. Tan, Dept. of Electron. Eng., Fudan Univ., Shanghai, China
J. Tong, Dept. of Electron. Eng., Fudan Univ., Shanghai, China
P. Tan, Dept. of Electron. Eng., Fudan Univ., Shanghai, China
N. Park, Dept. of Electron. Eng., Fudan Univ., Shanghai, China
F. Lombardi, Dept. of Electron. Eng., Fudan Univ., Shanghai, China
pp. 608
G. Tumbush, Dept. of Electron. Comput., Cincinnati Univ., OH, USA
D. Bhatia, Dept. of Electron. Comput., Cincinnati Univ., OH, USA
pp. 614
J.A. Chandy, Sierra Vista Res., Los Gatos, CA, USA
P. Banerjee, Sierra Vista Res., Los Gatos, CA, USA
pp. 621
Session 3.2.2: Design for Testability & Test Synthesis
K. Lai, Rockwell Semicond. Syst., Newport Beach, CA, USA
C.A. Papachristou, Rockwell Semicond. Syst., Newport Beach, CA, USA
M. Baklashov, Rockwell Semicond. Syst., Newport Beach, CA, USA
pp. 636
Jing-Yang Jou, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Ming-Chang Nien, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 642
R.C. Takumalla, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
P.R. Menon, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 648
M. Bacis, Dipt. di Elettronica, Politecnico di Milano, Italy
G. Buonanno, Dipt. di Elettronica, Politecnico di Milano, Italy
F. Ferrandi, Dipt. di Elettronica, Politecnico di Milano, Italy
F. Fummi, Dipt. di Elettronica, Politecnico di Milano, Italy
L. Gerli, Dipt. di Elettronica, Politecnico di Milano, Italy
D. Sciuto, Dipt. di Elettronica, Politecnico di Milano, Italy
pp. 654
Session 3.2.3: Embedded Tutorial
Session 3.2.4: Arithmetics
A. Meehrotra, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
S. Qadeer, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Ranjan, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.H. Katz, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 670
H. Suzuki, Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
H. Makino, Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
K. Mashiko, Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
H. Hamano, Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
pp. 685
Yamin Li, Comput. Archit. Lab., Univ. of Aizu, Japan
Wanming Chu, Comput. Archit. Lab., Univ. of Aizu, Japan
pp. 690
Session 3.3.1: Asynchronous Design
Maitham Shams, University of Waterloo
Mohamed I. Elmasry, University of Waterloo
Jo C. Ebergen, Sun Microsystems Laboratories
pp. 700
R. Kol, Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
R. Ginosar, Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
pp. 706
Wei Hwang, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R.V. Joshi, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
W.H. Henkels, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 712
Session 3.3.2: Special Session: Interconnect Modeling & Repeater Methodologies
Norman Chang, Hewlett-Packard Laboratories
Valery Kanevsky, Hewlett-Packard Laboratories
O. Sam Nakagawa, Hewlett-Packard Laboratories
Khalid Rahmat, Hewlett-Packard Laboratories
Soo-Young Oh, Hewlett-Packard Laboratories
pp. 720
D. Li, Texas Instrum. Inc., Dallas, TX, USA
A. Pua, Texas Instrum. Inc., Dallas, TX, USA
P. Srivastava, Texas Instrum. Inc., Dallas, TX, USA
U. Ko, Texas Instrum. Inc., Dallas, TX, USA
pp. 726
Zheng Zhu, Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
B.S. Carlson, Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
pp. 732
Session 3.3.3: Finite-State Machine and High-Level Synthesis
Chuan-Yu Wang, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 746
S. Govindarajan, Lab. for Digital Design Environ., Cincinnati Univ., OH, USA
R. Vemuri, Lab. for Digital Design Environ., Cincinnati Univ., OH, USA
pp. 752
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