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1996 IEEE International Conference on Computer Design (ICCD'96)
Austin, TX
October 07-October 09
ISBN: 0-8186-7554-3
Table of Contents
Session 1.3.1: Verification, Chair: Carl Pixley, Motorola, Inc.
Gianpiero Cabodi, Politecnico di Torino
Luciano Lavagno, Politecnico di Torino
Enrico Macii, Politecnico di Torino
Massimo Poncino, Politecnico di Torino
Stefano Quer, Politecnico di Torino
Paolo Camurati, Universita` di Udine
Ellen Sentovicha, Ecole des Mines de Paris
pp. 6
Session 1.3.2: Design for Test, Chair: Sumit Dasgupta, SEMATECH
D. Kagaris, Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
S. Tragoudas, Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 34
K. Arabi, Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
B. Kaminska, Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
S. Sunter, Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
pp. 40
Kamran Zarrineh, IBM Microelectronics Test Design Automation
Vivek Chickermane, IBM Microelectronics Test Design Automation
pp. 46
Session 1.3.3: Panel: Opportunities and Pitfalls in HDL-Based System Design
Session 1.3.4: Panel: Issues on the Architecture and the Design of Distributed Shared Memory Systems
Nian-Feng Tzeng, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
S.J. Wallach, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 60
D.E. Lenoski, Div. of Adv. Syst., Silicon Graphics Comput. Syst., Mountain View, CA, USA
pp. 62
D.A. Wood, Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
M.D. Hill, Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
J.R. Larus, Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 63
Session 1.4.1: Novel Aspects of Scheduling, Chair: Masahiro Fujeta, Fujitsu Laboratories of America, Inc.
Session 1.4.2: Special Session: Multimedia Systems, Chair and Organizer: Bing Sheu, University of Southern California
W. O'Connell, NCR Corp., Murray Hill, NJ, USA
G. Au, NCR Corp., Murray Hill, NJ, USA
D. Schrader, NCR Corp., Murray Hill, NJ, USA
pp. 86
W.M. Moh, Dept. of Math. & Comput. Sci., San Jose State Univ., CA, USA
Yu-Feng Chung, Dept. of Math. & Comput. Sci., San Jose State Univ., CA, USA
Teng-Sheng Moh, Dept. of Math. & Comput. Sci., San Jose State Univ., CA, USA
J. Wang, Dept. of Math. & Comput. Sci., San Jose State Univ., CA, USA
pp. 93
Session 1.4.3: System Design Aspects, Chair: Rabindra (Rob) Roy, NEC USA Research Laboratories
Kenneth Y. Yun, University of California, San Diego
Ryan P. Donohue, University of California, San Diego
pp. 118
Session 1.4.4: Panel
Processor Design Verification
Poster Session, Chair: Craig Hunter, Motorola, Inc.
N. Ben-Hamida, Ecole Polytech., Montreal, Que., Canada
B. Ayari, Ecole Polytech., Montreal, Que., Canada
B. Kaminska, Ecole Polytech., Montreal, Que., Canada
pp. 135
N. Ranganathan, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
N. Vijaykrishnan, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
N. Bhavanishankar, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
pp. 137
L. Alkalai, Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
Wai-Chi Fang, Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
pp. 141
Jin Li, Dept. of Adv. Archit. Dev., Adv. Micro Devices Inc., Austin, TX, USA
pp. 147
Session 2.1.1: Design and Test Plenary, Chair: Magdy Abadir, Motorola, Inc.
Session 2.2.1: Data Communication, Chair: John Trotter, AT&T Bell Laboratories
Jose L. Cruz-Rivera, University of Puerto Rico-Mayaguez
Scott Wills, Georgia Institute of Technology
Thomas Gaylord, Georgia Institute of Technology
Elias Glytsis, Georgia Institute of Technology
pp. 165
Session 2.2.2: Design Automation for Embedded Systems, Chair: Rolf Ernst, Technical University of Braunschweig
Session 2.2.3: Branch Prediction, Chair: Jim Bondi, Texas Instruments
Pradeep K. Dubey, IBM Thomas J. Watson Research Center
Ravi Nair, IBM Thomas J. Watson Research Center
pp. 217
Session 2.2.4: Automatic Test Pattern Generation, Chairs: Bob Molyneaux, IBM Corporation; Hoon Chang, Soong-Sil University of Korea
Session 2.3.1: VLSI Layout, Chair: Andreas Kuehlmann, IBM Corporation
Session 2.3.2: Special Session: Motorola Processor Design Session Chair: Nasr Ullah, Organizer: Andy Wolfe
Session 2.3.3: Embedded Systems Tutorial, Chair: Rolf Ernst, Technical University of Braunschweig
Session 2.3.4: VLSI Technology and Design, Chair: Kit Cham, Hewlett-Packard
Session 2.4.1: Panel
Processor Design Tools Integration: Future Challenges
Session 2.4.2: Panel
Session 3.1.1: Special Session, Chair: Wayne Wolf, Princeton University
Session 3.2.1: Verification II, Chair: Gabriel Bischoff, DAC
O. Thiry, IMEC, Katholieke Univ., Leuven, Belgium
L. Claesen, IMEC, Katholieke Univ., Leuven, Belgium
pp. 352
R.K. Ranjan, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
J.V. Sanghavi, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 358
F. Krohm, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
A. Kuchlmann, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
A. Mets, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 371
Session 3.2.2: Minimization Techniques, Chair: Shantanu Ganguly, Motorola, Inc.
R. Pendurkar, Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee, Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
C. Tovey, Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 396
Session 3.2.3: Panel
Influence of Internet Applications on Microarchitecture
Session 3.2.4: Future Asynchronous Designs, Chair: Larry Pileggi, Carnegie Mellon University
Session 3.3.1: Sequential Synthesis, Chair: Lukas van Ginneken, Synopsis, Inc.
Shaz Qadeer, University of California at Berkeley
Robert K. Brayton, University of California at Berkeley
Vigyan Singhal, Cadence Berkeley Labs
pp. 432
Session 3.3.2: Integration Support, Chair: Gabriel Bischoff, DAC
Session 3.3.3: Special Session
Performance Analysis and Validation
Bryan Black, Carnegie Mellon University
Andrew S. Huang, Carnegie Mellon University
Mikko H. Lipasti, Carnegie Mellon University
John Paul Shen, Carnegie Mellon University
pp. 478
A.-T. Nguyen, Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
M. Michael, Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
A. Sharma, Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
J. Torrellas, Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
pp. 486
Session 3.3.4: VLSI Signal Processors, Chair: Jacob A. Abraham, University of Texas at Austin
J.H. Satyanarayana, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Leilei Song, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Yun-Nam Chang, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 492
S.B. Aruru, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
N. Ranganathan, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
K.R. Namuduri, Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
pp. 500
Session 3.4.1: Architectural Issues in High Level Synthesis, Chair: Masahiro Fujita, Fujitsu Laboratories of America, Inc.
Session 3.4.2: Arithmetic Circuits, Chair: N. Ranganathan, University of South Florida
David R. Lutz, Bell Laboratories
D. N. Jayasimha, The Ohio State University
pp. 545
Session 3.4.4: Synthesis for FPGAs, Chair: Timothy Kam, Intel Corporation
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